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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
DS714 (v2.1) July 23, 2010 Product Specification
Virtex-5Q FPGA Electrical Characteristics
Defense-grade Virtex(R)-5Q FPGAs are available in -2I, -1I, and -1M (only FX70T and FX100T devices in -1M) speed grades, with -2I having the highest performance. Virtex-5Q FPGA DC and AC characteristics are specified for the industrial temperature range. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. This Virtex-5Q FPGA data sheet, part of an overall set of documentation on the Virtex-5 family of FPGAs, is available on the Xilinx website: * * * DS174, Virtex-5Q Family Overview UG190, Virtex-5 FPGA User Guide UG191, Virtex-5 FPGA Configuration Guide * * * * * * * * * UG192, Virtex-5 FPGA System Monitor User Guide UG193, Virtex-5 FPGA XtremeDSPTM Design Considerations User Guide UG194, Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide UG195, Virtex-5 FPGA Packaging and Pinout Specification UG196, Virtex-5 FPGA RocketIOTM GTP Transceiver User Guide UG197, Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express(R) Designs UG198, Virtex-5 FPGA RocketIO GTX Transceiver User Guide UG200, Embedded Processor Block in Virtex-5 FPGAs Reference Guide UG203, Virtex-5 FPGA PCB Designer's Guide
All specifications are subject to change without notice.
Virtex-5Q FPGA DC Characteristics
Table 1: Absolute Maximum Ratings(1)
Symbol
VCCINT VCCAUX VCCO VBATT VREF
Description
Internal supply voltage relative to GND Auxiliary supply voltage relative to GND Output drivers supply voltage relative to GND Key memory battery backup supply Input reference voltage 3.3V I/O input voltage relative to GND(2) (user and dedicated I/Os) I/Os)(4)
Range
-0.5 to 1.1 -0.5 to 3.0 -0.5 to 3.75 -0.5 to 4.05 -0.5 to 3.75 -0.75 to 4.05 -0.85 to 4.3
(Industrial Temperature)
Units
V V V V V V V V mA mA V V C
VIN(3)
3.3V I/O input voltage relative to GND (restricted to maximum of 100 user 2.5V or below I/O input voltage relative to GND (user and dedicated I/Os)
-0.75 to VCCO + 0.5 100 100 -0.75 to 4.05 -0.75 to VCCO + 0.5 -65 to 150
IIN VTS TSTG
Current applied to an I/O pin, powered or unpowered Total current applied to all I/O pins, powered or unpowered Voltage applied to 3-state 3.3V output(2) (user and dedicated I/Os) Voltage applied to 3-state 2.5V or below output (user and dedicated I/Os) Storage temperature (ambient)
(c) 2009-2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 1: Absolute Maximum Ratings(1) (Cont'd)
Symbol
TSOL Tj Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. For 3.3V I/O operation, refer to Virtex-5 FPGA User Guide, Chapter 6, 3.3V I/O Design Guidelines. 3.3V I/O absolute maximum limit applied to DC and AC signals. For more flexibility in specific designs, a maximum of 100 user I/Os can be stressed beyond the normal specification for no more than 20% of a data period. For soldering guidelines, refer to UG112: Device Package User Guide. For thermal considerations, refer to UG195: Virtex-5 FPGA Packaging and Pinout Specification on the Xilinx website.
Description
Maximum soldering Maximum junction temperature(5) temperature(5)
Range
+220 +125
Units
C C
2. 3. 4. 5.
Table 2: Recommended Operating Conditions
Symbol
VCCINT VCCAUX(1) VCCO(2, 3, 4) VIN
Description
Internal supply voltage relative to GND, Tj = -40C to +100C Auxiliary supply voltage relative to GND, Tj = -40C to +100C Supply voltage relative to GND, Tj = -40C to +100C 3.3V supply voltage relative to GND, Tj = -40C to +100C 2.5V and below supply voltage relative to GND, Tj = -40C to +100C
Temperature Range
Industrial Industrial Industrial Industrial Industrial Industrial Industrial
Min
0.95 2.375 1.14 GND - 0.20 GND - 0.20
Max
1.05 2.625 3.45 3.45 VCCO + 0.2 10
Units
V V V V V mA V
IIN VBATT(5) Notes:
1. 2. 3. 4. 5.
Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. Battery voltage relative to GND, Tj = -40C to +100C
1.0
3.6
Recommended maximum voltage drop for VCCAUX is 10 mV/ms. Configuration data is retained even if VCCO drops to 0V. Includes VCCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V. The configuration supply voltage VCC_CONFIG is also known as VCCO_0. VBATT is required only when using bitstream encryption. If battery is not used, connect VBATT to either ground or VCCAUX.
Table 3: DC Characteristics Over Recommended Operating Conditions
Symbol
VDRINT VDRI IREF IL CIN IRPU(1)
Description
Data retention VCCINT voltage (below which configuration data might be lost) Data retention VCCAUX voltage (below which configuration data might be lost) VREF leakage current per pin Input or output leakage current per pin (sample-tested) Input capacitance (sample-tested) Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V
Min
0.75 2.0
Typ
Max
Units
V V
10 10 8 20 10 5 3 2 5 1.0002 5.0 150 90 45 30 15 110 150
A A pF A A A A A A nA n
IRPD(1) IBATT(2) n r Notes:
1. 2.
Pad pull-down (when selected) @ VIN = 2.5V Battery supply current Temperature diode ideality factor Series resistance
Typical values are specified at nominal voltage, 25C. Maximum value specified for worst case process at 25C.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Important Note
Typical values for quiescent supply current are now specified at nominal voltage, 85C junction temperatures (Tj). Xilinx recommends analyzing static power consumption at Tj = 85C because the majority of designs operate near the high end of the commercial temperature range. Data sheets for older products (e.g., Virtex-4 devices) still specify typical quiescent supply current at Tj = 25C. Quiescent supply current is specified by speed grade for Virtex-5Q devices. Use the XPOWER Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to calculate static power consumption for conditions other than those specified in Table 4. Table 4: Typical Quiescent Supply Current
Symbol
ICCINTQ
Description
Quiescent VCCINT supply current
Device
XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T
Speed and Temperature Grade -2 (I)
507 1072 1391 1448 2674 2844 N/A 1092 1924 N/A 1658 2875 3041 N/A 1.5 3 4 4 8 8 N/A 2 4 N/A 6 7 8 N/A
-1 (I)
317 833 1109 1154 2188 2328 3492 840 1475 3168 1658 2875 3041 3755 1.5 3 4 4 8 8 12 2 4 12 6 7 8 10
-1 (M)
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 1658 2875 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 6 7 N/A N/A
Units
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
ICCOQ
Quiescent VCCO supply current
XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 4: Typical Quiescent Supply Current (Cont'd)
Symbol
ICCAUXQ
Description
Quiescent VCCAUX supply current
Device
XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T
Speed and Temperature Grade -2 (I)
43 93 125 130 177 236 N/A 74 131 N/A 110 150 180 N/A
-1 (I)
43 93 125 130 177 236 353 74 131 300 110 150 180 250
-1 (M)
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 110 150 N/A N/A
Units
mA mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes:
1. Typical values are specified at nominal voltage, 85C junction temperatures (Tj). Industrial (I) and Military (M) grade devices have the same typical values as commercial (C) grade devices at 85C, but higher values at 100C (I) and 125C (M). Use the XPE/XPA power tools to calculate values for conditions other than specified in this data sheet. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools.
2. 3.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device initialization. The actual current consumed depends on the power-on ramp rate of the power supply. The power supplies can be turned on in any sequence, though the specifications shown in Table 5 are for the recommended power-on sequence of VCCINT, VCCAUX, and VCCO. The I/O will remain 3-stated through power-on if the recommended power-on sequence is followed. Xilinx does not specify the current or I/O behavior for other power-on sequences. Table 5 shows the minimum current required by Virtex-5Q devices for proper power-on and configuration. If the current minimums shown in Table 5 are met, the device powers on properly after all three supplies have passed through their power-on reset threshold voltages. The FPGA must be configured after VCCINT is applied. Once initialized and configured, use the XPOWER tools to estimate current drain on these supplies. Table 5: Power-On Current for Virtex-5Q Devices
Device
XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T Notes:
1. 2. Typical values are specified at nominal voltage, 25C. The maximum startup current can be obtained using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools and adding the quiescent plus dynamic current consumption.
ICCINTMIN Typ(1)
246 492 623 651 728 1056 1509 472 804 1632 695 749 1111 1222
ICCAUXMIN Typ(1)
86 186 250 260 368 472 706 148 262 662 232 298 392 534
ICCOMIN Typ(1)
50 100 100 100 100 150 150 50 100 150 100 100 150 150
Units
mA mA mA mA mA mA mA mA mA mA mA mA mA mA
Table 6: Power Supply Ramp Time
Symbol
VCCINT VCCO VCCAUX
Description
Internal supply voltage relative to GND Output drivers supply voltage relative to GND Auxiliary supply voltage relative to GND
Ramp Time
0.20 to 50.0 0.20 to 50.0 0.20 to 50.0
Units
ms ms ms
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
SelectIOTM DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Table 7: SelectIO DC Input and Output Levels
I/O Standard
LVTTL LVCMOS33, LVDCI33 LVCMOS25, LVDCI25 LVCMOS18, LVDCI18 LVCMOS15, LVDCI15 LVCMOS12 PCI33_3(5) PCI66_3(5) PCI-X(5) GTLP GTL HSTL I_12 HSTL I(2) HSTL HSTL II(2) III(2) I(2) II(2)
VIL V, Min
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.2 -0.2 -0.2 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
VIH V, Max
0.8 0.8 0.7
VOL V, Max
3.45 3.45 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO VCCO VCCO - - VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3
VOH V, Min
2.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.45 75% VCCO 75% VCCO 90% VCCO 90% VCCO 90% VCCO - - 75% VCCO VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 - - VTT + 0.61 VTT + 0.81 - - VTT + 0.47 VTT + 0.60 - -
IOL mA
Note(3) Note(3) Note(3) Note(4) Note(4) Note(6) Note(5) Note(5) Note(5) 36 32 6.3 8 16 24 48 - - 8.1 16.2 - - 6.7 13.4 - -
IOH mA
Note(3) Note(3) Note(3) Note(4) Note(4) Note(6) Note(5) Note(5) Note(5) - - 6.3 -8 -16 -8 -8 - - -8.1 -16.2 - - -6.7 -13.4 - -
V, Min
2.0 2.0 1.7 65% VCCO 65% VCCO 65% VCCO 50% VCCO 50% VCCO 50% VCCO VREF + 0.1 VREF + 0.05 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1
V, Max
0.4 0.4 0.4 0.45 25% VCCO 25% VCCO 10% VCCO 10% VCCO 10% VCCO 0.6 0.4 25% VCCO 0.4 0.4 0.4 0.4 - - VTT - 0.61 VTT - 0.81 - - VTT - 0.47 VTT - 0.60 - -
35% VCCO 35% VCCO 35% VCCO 30% VCCO 30% VCCO 35% VCCO VREF - 0.1 VREF - 0.05 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1
HSTL IV(2) DIFF HSTL DIFF HSTL SSTL2 I SSTL2 II DIFF SSTL2 I DIFF SSTL2 II SSTL18 I SSTL18 II DIFF SSTL18 I DIFF SSTL18 II Notes:
1. 2. 3. 4. 5. 6.
50% VCCO - 0.1 50% VCCO + 0.1 50% VCCO - 0.1 50% VCCO + 0.1 VREF - 0.15 VREF - 0.15 50% VCCO - 0.15 50% VCCO - 0.15 VREF - 0.125 VREF - 0.125 50% VCCO - 0.125 50% VCCO - 0.125 VREF + 0.15 VREF + 0.15 50% VCCO + 0.15 50% VCCO + 0.15 VREF + 0.125 VREF + 0.125 50% VCCO + 0.125 50% VCCO + 0.125
Tested according to relevant specifications. Applies to both 1.5V and 1.8V HSTL. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA. For more information on PCI33_3, PCI66_3, and PCI-X, refer to Virtex-5 FPGA User Guide, Chapter 6, 3.3V I/O Design Guidelines. Supported drive strengths of 2, 4, 6, or 8 mA.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
HT DC Specifications (HT_25)
Table 8: HT DC Specifications
Symbol
VCCO VOD VOD VOCM VOCM VID VID VICM VICM
DC Parameter
Supply Voltage Differential Output Voltage Change in VOD Magnitude Output Common Mode Voltage Change in VOCM Magnitude Input Differential Voltage Change in VID Magnitude Input Common Mode Voltage Change in VICM Magnitude
Conditions
Min
2.38
Typ
2.5 600
Max
2.63 840 15
Units
V mV mV mV mV mV mV mV mV
RT = 100 across Q and Q signals RT = 100 across Q and Q signals
495 -15 495 -15 200 -15 440 -15
600
715 15
600
1000 15
600
780 15
LVDS DC Specifications (LVDS_25)
Table 9: LVDS DC Specifications
Symbol
VCCO VOH VOL VODIFF VOCM VIDIFF VICM
DC Parameter
Supply Voltage Output High Voltage for Q and Q Output Low Voltage for Q and Q Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High Output Common-Mode Voltage Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High Input Common-Mode Voltage
Conditions
Min
2.38
Typ
2.5
Max
2.63 1.675
Units
V V V
RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals 0.825 247 1.125 100 0.3 350 1.250 350 1.2
600 1.375 600 2.2
mV V mV V
Extended LVDS DC Specifications (LVDSEXT_25)
Table 10: Extended LVDS DC Specifications
Symbol
VCCO VOH VOL VODIFF VOCM VIDIFF VICM
DC Parameter
Supply Voltage Output High Voltage for Q and Q Output Low Voltage for Q and Q Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High Output Common-Mode Voltage Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High Input Common-Mode Voltage
Conditions
Min
2.38
Typ
2.5 -
Max
2.63 1.785 - 820 1.475 1000 2.2
Units
V V V mV V mV V
RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals Common-mode input voltage = 1.25V Differential input voltage = 350 mV 0.715 350 1.025 100 0.3
- - 1.250 - 1.2
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
LVPECL DC Specifications (LVPECL_25)
These values are valid when driving a 100 differential load only, i.e., a 100 resistor between the two receiver pins. The VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode ranges. Table 11 summarizes the DC output specifications of LVPECL. For more information on using LVPECL, see Virtex-5 FPGA User Guide, Chapter 6, SelectIO Resources. Table 11: LVPECL DC Specifications
Symbol
VOH VOL VICM VIDIFF Notes:
1. 2. Recommended input maximum voltage not to exceed VCCAUX + 0.2V. Recommended input minimum voltage not to go below -0.5V.
DC Parameter
Output High Voltage Output Low Voltage Input Common-Mode Voltage Differential Input Voltage(1,2)
Min
VCC - 1.025 VCC - 1.81 0.6 0.100
Typ
1.545 0.795
Max
VCC - 0.88 VCC - 1.62 2.2 1.5
Units
V V V V
PowerPC 440 Switching Characteristics
Consult the Embedded Processor Block in Virtex-5 FPGAs Reference Guide for further information. Table 12: Processor Block Switching Characteristics
Clock Name
CPMC440CLK CPMINTERCONNECTCLK CPMPPCS0PLBCLK CPMPPCS1PLBCLK CPMPPCMPLBCLK CPMMCCLK CPMFCMCLK CPMDCRCLK CPMDMA0LLCLK CPMDMA1LLCLK CPMDMA2LLCLK CPMDMA3LLCLK JTGC440TCK CPMC440TIMERCLOCK Notes:
1. 2. Typical bus frequencies are provided for reference only, actual frequencies are user-design dependent. Refer to DS567, DDR2 Memory Controller for PowerPC 440 Processors, for maximum clock speed of designs using the DDR2 Memory Controller for PowerPC(R) 440 processors.
Description
CPU clock Xbar clock Slave 0 PLB Slave 1 PLB Master PLB clock(1) clock(1) clock(1) clock(1, 2) clock(1)
Speed Grade -2I
475 316.6 158.3 158.3 158.3 316.6 237.5 158.3 250 250 250 250 50 237.5
-1I
400 266.6 133.3 133.3 133.3 266.6 200 133.3 200 200 200 200 50 200
-1M
400 266.6 133.3 133.3 133.3 266.6 200 133.3 200 200 200 200 50 200
Units
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Memory interface FCM clock(1) clock(1) clock(1) clock(1) clock(1)
FPGA logic DCR DMA0 LL DMA1 LL DMA2 LL DMA3 LL
JTAG clock Timer clock
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 13: Processor Block MIB Switching Characteristics
Clock Name Clock-to-out and setup relative to clock
TCK_CONTROL TCK_ADDRESS TCK_DATA TCONTROL_CK TDATA_CK CPMMCCLK CPMMCCLK CPMMCCLK CPMMCCLK CPMMCCLK 1.247 1.136 1.172 0.844 0.95 1.463 1.38 1.38 0.941 1.058 1.463 1.38 1.38 0.941 1.058 ps ps ps ps ps
Reference Clock
Speed Grade -2I -1I -1M
Units
Table 14: Processor Block PLBM Switching Characteristics
Clock Name Clock-to-out and setup relative to clock
TCK_CONTROL TCK_ADDRESS TCK_DATA TCONTROL_CK TDATA_CK CPMPPCMPLBCLK CPMPPCMPLBCLK CPMPPCMPLBCLK CPMPPCMPLBCLK CPMPPCMPLBCLK 1.095 1.372 1.257 1.79 0.914 1.354 1.673 1.535 1.86 1.059 1.354 1.673 1.535 1.86 1.059 ps ps ps ps ps
Reference Clock
Speed Grade -2I -1I -1M
Units
Table 15: Processor Block PLBS0 Switching Characteristics
Clock Name Clock-to-out and setup relative to clock
TCK_CONTROL TCK_DATA TCONTROL_CK TADDRESS_CK TDATA_CK CPMPPCS0PLBCLK CPMPPCS0PLBCLK CPMPPCS0PLBCLK CPMPPCS0PLBCLK CPMPPCS0PLBCLK 1.196 1.189 1.545 1.492 0.971 1.462 1.461 1.836 1.787 1.124 1.462 1.461 1.836 1.787 1.124 ps ps ps ps ps
Reference Clock
Speed Grade -2I -1I -1M
Units
Table 16: Processor Block PLBS1 Switching Characteristics
Clock Name Clock-to-out and setup relative to clock
TCK_CONTROL TCK_DATA TCONTROL_CK TADDRESS_CK TDATA_CK CPMPPCS1PLBCLK CPMPPCS1PLBCLK CPMPPCS1PLBCLK CPMPPCS1PLBCLK CPMPPCS1PLBCLK 1.234 1.298 1.596 1.568 0.969 1.525 1.615 1.921 1.864 1.127 1.525 1.615 1.921 1.864 1.127 ps ps ps ps ps
Reference Clock
Speed Grade -2I -1I -1M
Units
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 17: Processor Block DMA0 Switching Characteristics
Clock Name Clock-to-out and setup relative to clock
TCK_CONTROL TCK_DATA TCONTROL_CK TDATA_CK CPMDMA0LLCLK CPMDMA0LLCLK CPMDMA0LLCLK CPMDMA0LLCLK 1.42 1.472 0.558 -0.105 1.665 1.712 0.716 -0.104 1.665 1.712 0.716 -0.104 ps ps ps ps
Reference Clock
Speed Grade -2I -1I -1M
Units
Table 18: Processor Block DMA1 Switching Characteristics
Clock Name Clock-to-out and setup relative to clock
TCK_CONTROL TCK_DATA TCONTROL_CK TDATA_CK CPMDMA1LLCLK CPMDMA1LLCLK CPMDMA1LLCLK CPMDMA1LLCLK 1.266 1.418 0.555 0.01 1.474 1.645 0.717 0.046 1.474 1.645 0.717 0.046 ps ps ps ps
Reference Clock
Speed Grade -2I -1I -1M
Units
Table 19: Processor Block DMA2 Switching Characteristics
Clock Name Clock-to-out and setup relative to clock
TCK_CONTROL TCK_DATA TCONTROL_CK TDATA_CK CPMDMA2LLCLK CPMDMA2LLCLK CPMDMA2LLCLK CPMDMA2LLCLK 1.235 1.262 0.924 0.142 1.437 1.463 1.155 0.168 1.437 1.463 1.155 0.168 ps ps ps ps
Reference Clock
Speed Grade -2I -1I -1M
Units
Table 20: Processor Block DMA3 Switching Characteristics
Clock Name Clock-to-out and setup relative to clock
TCK_CONTROL TCK_DATA TCONTROL_CK TDATA_CK CPMDMA3LLCLK CPMDMA3LLCLK CPMDMA3LLCLK CPMDMA3LLCLK 1.242 1.184 0.767 0.119 1.462 1.376 0.965 0.116 1.462 1.376 0.965 0.116 ps ps ps ps
Reference Clock
Speed Grade -2I -1I -1M
Units
Table 21: Processor Block DCR Switching Characteristics
Clock Name Clock-to-out and setup relative to clock
TCK_CONTROL TCK_ADDRESS TCK_DATA TCONTROL_CK TADDRESS_CK TDATA_CK CPMDCRCLK CPMDCRCLK CPMDCRCLK CPMDCRCLK CPMDCRCLK CPMDCRCLK - - - - - - - - - - - - - - - - - -
Reference Clock
Speed Grade -2I -1I -1M
Units
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 22: Processor Block FCM Switching Characteristics
Clock Name Clock-to-out and setup relative to clock
TCK_CONTROL TCK_DATA TCK_INSTRUCTION TCONTROL_CK TDATA_CK TRESULT_CK CPMFCMCLK CPMFCMCLK CPMFCMCLK CPMFCMCLK CPMFCMCLK CPMFCMCLK 1.084 1.158 0.818 1.218 0.698 0.698 1.324 1.4 1.06 1.395 0.768 0.768 1.324 1.4 1.06 1.395 0.768 0.768 ps ps ps ps ps ps
Reference Clock
Speed Grade -2I -1I -1M
Units
Table 23: Processor Block MISC Switching Characteristics
Clock Name Clock-to-out and setup relative to clock
TCK_CONTROL TCK_ADDRESS TCK_DATA TCONTROL_CK TADDRESS_CK TDATA_CK CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 - - - - - - - - - - - - - - - - - -
Reference Clock
Speed Grade -2I -1I -1M
Units
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
GTP_DUAL Tile Specifications
GTP_DUAL Tile DC Characteristics
Table 24: Absolute Maximum Ratings for GTP_DUAL Tiles
Symbol
MGTAVCCPLL MGTAVTTTX MGTAVTTRX MGTAVCC MGTAVTTRXC Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Description
Analog supply voltage for the GTP_DUAL shared PLL relative to GND Analog supply voltage for the GTP_DUAL transmitters relative to GND Analog supply voltage for the GTP_DUAL receivers relative to GND Analog supply voltage for the GTP_DUAL common circuits relative to GND Analog supply voltage for the resistor calibration circuit of the GTP_DUAL column -0.5 to 1.32 -0.5 to 1.32 -0.5 to 1.32 -0.5 to 1.1 -0.5 to 1.32
Units
V V V V V
Table 25: Recommended Operating Conditions for GTP_DUAL Tiles(1, 2)
Symbol
MGTAVCCPLL(1) MGTAVTTTX(1) MGTAVTTRX(1) MGTAVCC(1) MGTAVTTRXC(1) Notes:
1. 2. Each voltage listed requires the filter circuit described in Virtex-5 FPGA RocketIO GTP Transceiver User Guide. Voltages are specified for the temperature range of Tj = -40C to +100C.
Description
Analog supply voltage for the GTP_DUAL shared PLL relative to GND Analog supply voltage for the GTP_DUAL transmitters relative to GND Analog supply voltage for the GTP_DUAL receivers relative to GND Analog supply voltage for the GTP_DUAL common circuits relative to GND Analog supply voltage for the resistor calibration circuit of the GTP_DUAL column
Min
1.14 1.14 1.14 0.95 1.14
Max
1.26 1.26 1.26 1.05 1.26
Units
V V V V V
Table 26: DC Characteristics Over Recommended Operating Conditions for GTP_DUAL Tiles(1)
Symbol
IMGTAVTTTX IMGTAVCCPLL IMGTAVTTRXC IMGTAVTTRX IMGTAVCC MGTRREF Notes:
1. 2. 3. Typical values are specified at nominal voltage, 25C, with a 3.2 Gb/s line rate. ICC numbers are given per GTP_DUAL tile with both GTP transceivers operating with default settings. AC coupled TX/RX link.
Description
GTP_DUAL tile transmitter termination supply current(2) GTP_DUAL tile shared PLL supply current GTP_DUAL tile resistor termination calibration supply current GTP_DUAL tile receiver termination supply current(3) GTP_DUAL tile internal analog supply current Precision reference resistor for internal calibration termination
Min
Typ
71 36 0.1 0.1 56
Max
90 60 0.5 0.5 110
Units
mA mA mA mA mA
49.9 1% tolerance
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 27: GTP_DUAL Tile Quiescent Supply Current
Symbol
IAVTTTXQ IAVCCPLLQ IAVTTRXQ IAVCCQ Notes:
1. 2. 3. 4. Typical values are specified at nominal voltage, 25C. Device powered and unconfigured. Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools. GTP_DUAL tile quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of available GTP_DUAL tiles in the target LXT or SXT device.
Description
Quiescent MGTAVTTTX (transmitter termination) supply current Quiescent MGTAVCCPLL (PLL) supply current Quiescent MGTAVTTRX (receiver termination) supply current. Includes MGTAVTTRXCQ. Quiescent MGTAVCC (analog) supply current
Typ(1)
8.5 8 0.1 2.5
Max
18 18 0.8 11
Units
mA mA mA mA
GTP_DUAL Tile DC Input and Output Levels
Table 28 summarizes the DC output specifications of the GTP_DUAL tiles in Virtex-5Q FPGAs. Figure 1, page 14 shows the single-ended output voltage swing. Figure 2, page 14 shows the peak-to-peak differential output voltage. Consult Virtex-5 FPGA RocketIO GTP Transceiver User Guide for further details. Table 28: GTP_DUAL Tile DC Specifications
Symbol DC Parameter
Differential peak-to-peak input voltage
Conditions
External AC coupled 3.2 Gb/s External AC coupled > 3.2 Gb/s DC coupled DC coupled MGTAVTTRX = 1.2V TXBUFDIFFCTRL = 000, TX_DIFF_BOOST = ON TXBUFDIFFCTRL = 000, TX_DIFF_BOOST = ON Equation based MGTAVTTTX = 1.2V
Min
150 180
Typ
Max
2000 2000 MGTAVTTRX + 400 up to 1320
Units
mV mV
DVPPIN
VIN VCMIN DVPPOUT VSEOUT VCMOUT RIN ROUT TOSKEW CEXT Notes:
1. 2.
Absolute input voltage
-400
mV
Common mode input voltage Differential peak-to-peak output voltage (1) Single-ended output voltage swing (1) Common mode output voltage Differential input resistance Differential output resistance Transmitter output skew
800 1400 700 1200 - Amplitude/2 90 90 100 100 120 120 15 75 100 200
mV mV mV mV ps nF
Recommended external AC coupling capacitor(2)
The output swing and preemphasis levels are programmable using the attributes discussed in Virtex-5 FPGA RocketIO GTP Transceiver User Guide and can result in values lower than reported in this table. Values outside of this range can be used as appropriate to conform to specific protocols and standards.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
X-Ref Target - Figure 1
+V
P VSEOUT
ds714_01_012109
N 0
Figure 1: Single-Ended Output Voltage Swing
X-Ref Target - Figure 2
+V
0
DVPPOUT DVPPIN
-V
P-N
ds714_02_012109
Figure 2: Peak-to-Peak Differential Output Voltage Table 29 summarizes the DC specifications of the clock input of the GTP_DUAL tile. Figure 3 shows the single-ended input voltage swing. Figure 4 shows the peak-to-peak differential clock input voltage swing. Consult Virtex-5 FPGA RocketIO GTP Transceiver User Guide for further details. Table 29: GTP_DUAL Tile Clock DC Input Specifications(1)
Symbol
VIDIFF VISE RIN CEXT Notes:
1. VMIN = 0V and VMAX = 1200 mV
DC Parameter
Differential peak-to-peak input voltage Single-ended input voltage Differential input resistance Required external AC coupling capacitor
Conditions
Min
200 100 80 75
Typ
800 400 105 100
Max
2000 1000 130 200
Units
mV mV nF
X-Ref Target - Figure 3
+V
P
VISE
N
0
Figure 3: Single-Ended Clock Input Voltage Swing Peak-to-Peak
X-Ref Target - Figure 4
ds714_03_012109
+V
P-N
0
VIDIFF
-V
ds714_04_012109
Figure 4: Differential Clock Input Voltage Swing Peak-to-Peak
DS714 (v2.1) July 23, 2010 Product Specification www.xilinx.com 14
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
GTP_DUAL Tile Switching Characteristics
Consult Virtex-5 FPGA RocketIO GTP Transceiver User Guide for further information. Table 30: GTP_DUAL Tile Performance
Symbol
FGTPMAX FGPLLMAX FGPLLMIN
Description
Maximum GTP transceiver data rate Maximum PLL frequency Minimum PLL frequency
Speed Grade -2I
3.75 2.0 1.0
-1I
3.2 2.0 1.0
Units
Gb/s GHz GHz
Table 31: Dynamic Reconfiguration Port (DRP) in the GTP_DUAL Tile Switching Characteristics
Symbol
FGTPDRPCLK GTPDRPCLK maximum frequency
Description
Speed Grade -2I
175
-1I
150
Units
MHz
Table 32: GTP_DUAL Tile Reference Clock Switching Characteristics
Symbol FGCLK TRCLK TFCLK TDCREF TGJTT TLOCK TPHASE Description Reference clock frequency range(1) CLK Reference clock rise time Reference clock fall time Reference clock duty cycle(2) 20% - 80% 80% - 20% CLK CLK Initial PLL lock Lock to data after PLL has locked to the reference clock 40 Conditions All Speed Grades Min 60 200 200 50 Typ Max 350 400 400 60 40 1 200 Units MHz ps ps % ps ms s
Reference clock total jitter, peakpeak (3) Clock recovery frequency acquisition time Clock recovery phase acquisition time
Notes: 1. The clock from the GTP_DUAL differential clock pin pair can be used for all serial bit rates. GREFCLK can be used for serial bit rates up to 1 Gb/s. 2. For reference clock rates above 325 MHz, a duty cycle of 45% to 55% must be maintained. 3. Measured at the package pin. GTP_DUAL jitter characteristics measured using a clock with specification TGJTT.
X-Ref Target - Figure 5
TRCLK
80%
20%
TFCLK
ds714_05_012109
Figure 5: Reference Clock Timing Parameters
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 33: GTP_DUAL Tile User Clock Switching Characteristics(1)
Symbol FTXOUT FRXREC TRX TRX2 TTX TTX2 Description TXOUTCLK maximum frequency RXRECCLK maximum frequency RXUSRCLK maximum frequency RXUSRCLK2 maximum frequency TXUSRCLK maximum frequency TXUSRCLK2 maximum frequency TXDATAWIDTH = 0 TXDATAWIDTH = 1 RXDATAWIDTH = 0 RXDATAWIDTH = 1 Conditions Speed Grade
-2I
375 375 375 350 187.5 375 350 187.5
-1I
320 320 320 320 160 320 320 160
Units MHz MHz MHz MHz MHz MHz MHz MHz
Notes: 1. Clocking must be implemented as described in Virtex-5 FPGA RocketIO GTP Transceiver User Guide.
Table 34: GTP_DUAL Tile Transmitter Switching Characteristics
Symbol
FGTPTX TRTX TFTX TLLSKEW VTXOOBVDPP TTXOOBTRANS TJ3.75 DJ3.75 TJ3.2 DJ3.2 TJ2.5 DJ2.5 TJ2.0 DJ2.0 TJ1.25 DJ1.25 TJ1.00 DJ1.00 TJ500 DJ500 TJ100 DJ100 Serial data rate range TX Rise time TX Fall time TX lane-to-lane skew(1) Electrical idle amplitude Electrical idle transition time Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) 3.75 Gb/s
Description
Min
0.1
Typ
Max
FGTPMAX
Units
Gb/s ps ps
140 120 855 20 40 0.35 0.19 0.35 0.19 0.30 0.14 0.30 0.14 0.20 0.10 0.20 0.10 0.10 0.04 0.02 0.01
ps mV ns UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI
3.20 Gb/s
2.50 Gb/s
2.00 Gb/s
1.25 Gb/s
1.00 Gb/s
500 Mb/s
100 Mb/s
Notes: 1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP_DUAL sites. 2. Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. 3. All jitter values are based on a Bit-Error Ratio of 1e-12.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 35: GTP_DUAL Tile Receiver Switching Characteristics
Symbol
FGTPRX RXOOBVDPP RXSST RXRL Serial data rate OOB detect threshold peak-to-peak Receiver spread-spectrum tracking(1) Run length (CID)
Description
RX oversampler not enabled RX oversampler enabled OOBDETECT_THRESHOLD = 100 Modulated @ 33 KHz Internal AC capacitor bypassed loop disabled with CDR PLL_RXDIVSEL_OUT = 1(2) 2nd-order
Min
0.5 0.1 60 -5000
Typ
Max
FGTPMAX 0.5
Units
Gb/s Gb/s mV ppm UI ppm ppm ppm ppm
105
165 0 150
-200 -200 -100 -1000
200 200 100 1000
RXPPMTOL
Data/REFCLK PPM offset tolerance
CDR 2nd-order loop disabled with PLL_RXDIVSEL_OUT = 2(2) CDR 2nd-order loop disabled with PLL_RXDIVSEL_OUT = 4(2) CDR 2nd-order loop enabled
SJ Jitter Tolerance
JT_SJ3.75 JT_SJ3.2 JT_SJ2.50 JT_SJ2.00 JT_SJ1.00 JT_SJ500 JT_SJ500 JT_SJ100 Sinusoidal Jitter(3) Sinusoidal Jitter(3) Sinusoidal Jitter(3) Sinusoidal Jitter(3) Sinusoidal Jitter(3) Sinusoidal Jitter(3) Sinusoidal Jitter(3) Sinusoidal Jitter(3) 3.75 Gb/s 3.20 Gb/s 2.50 Gb/s 2.00 Gb/s 1.00 Gb/s 500 Mb/s 500 Mb/s OS 100 Mb/s OS 0.30 0.40 0.40 0.40 0.30 0.30 0.30 0.30 UI UI UI UI UI UI UI UI
SJ Jitter Tolerance with Stressed Eye
JT_TJSE3.2 JT_SJSE3.2 Notes:
1. 2. 3. 4. 5. Using PLL_RXDIVSEL_OUT = 1 only. CDR 1st-order step size set to 2. Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter. Stimulus signal includes 0.4UI of DJ and 0.17UI of RJ. RX equalizer is enabled. All jitter values are based on a Bit Error Ratio of 1e-12.
Total Jitter with Stressed Eye(4) Sinusoidal Jitter with Stressed Eye(4)
3.20 Gb/s 3.20 Gb/s
0.87 0.30
UI UI
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
GTX_DUAL Tile Specifications
GTX_DUAL Tile DC Characteristics
Table 36: Absolute Maximum Ratings for GTX_DUAL Tiles
Symbol
MGTAVCCPLL MGTAVTTTX MGTAVTTRX MGTAVCC MGTAVTTRXC Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Description
Analog supply voltage for the GTX_DUAL shared PLL relative to GND Analog supply voltage for the GTX_DUAL transmitters relative to GND Analog supply voltage for the GTX_DUAL receivers relative to GND Analog supply voltage for the GTX_DUAL common circuits relative to GND Analog supply voltage for the resistor calibration circuit of the GTX_DUAL column -0.5 to 1.1 -0.5 to 1.32 -0.5 to 1.32 -0.5 to 1.1 -0.5 to 1.32
Units
V V V V V
Table 37: Recommended Operating Conditions for GTX_DUAL Tiles(1, 2)
Symbol
MGTAVCCPLL(1) MGTAVTTTX(1) MGTAVTTRX(1) MGTAVCC(1) MGTAVTTRXC(1) Notes:
1. 2. Each voltage listed requires the filter circuit described in Virtex-5 FPGA RocketIO GTX Transceiver User Guide. Voltages are specified for the temperature range of Tj = -40C to +100C.
Description
Analog supply voltage for the GTX_DUAL shared PLL relative to GND Analog supply voltage for the GTX_DUAL transmitters relative to GND Analog supply voltage for the GTX_DUAL receivers relative to GND Analog supply voltage for the GTX_DUAL common circuits relative to GND Analog supply voltage for the resistor calibration circuit of the GTX_DUAL column
Min
0.95 1.14 1.14 0.95 1.14
Max
1.05 1.26 1.26 1.05 1.26
Units
V V V V V
Table 38: DC Characteristics Over Recommended Operating Conditions for GTX_DUAL Tiles(1)
Symbol
IMGTAVTTTX IMGTAVCCPLL IMGTAVTTRXC IMGTAVTTRX IMGTAVCC MGTRREF Notes:
1. 2. 3. 4. Typical values are specified at nominal voltage, 25C, with a 3.2 Gb/s line rate. ICC numbers are given per GTX_DUAL tile with both GTX transceivers operating with default settings. AC coupled TX/RX link. Values for currents other than the values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools.
Description
GTX_DUAL tile transmitter termination supply current(2) GTX_DUAL tile shared PLL supply current GTX_DUAL tile resistor termination calibration supply current GTX_DUAL tile receiver termination supply current(3) GTX_DUAL tile internal analog supply current Precision reference resistor for internal calibration termination
Min
Typ
43.3 38.0 0.1 40.3 80.5
Max
86.3 99.4 0.5 56.5 179.5
Units
mA mA mA mA mA
59.0 1% tolerance
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 39: GTX_DUAL Tile Quiescent Supply Current
Symbol
IAVTTTXQ IAVCCPLLQ IAVTTRXQ IAVCCQ
Description
Quiescent MGTAVTTTX (transmitter termination) supply current Quiescent MGTAVCCPLL (PLL) supply current Quiescent MGTAVTTRX (receiver termination) supply current. Includes MGTAVTTRXCQ. Quiescent MGTAVCC (analog) supply current
Typ(1)
8.2 0.8 1.2 9.0
Max
21.6 4.8 12.0 50.4
Units
mA mA mA mA
Notes: 1. Typical values are specified at nominal voltage, 25C. 2. Device powered and unconfigured. 3. Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools. 4. GTX_DUAL tile quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of available GTX_DUAL tiles in the target FXT device.
GTX_DUAL Tile DC Input and Output Levels
Table 40 summarizes the DC output specifications of the GTX_DUAL tiles in Virtex-5Q FPGAs. Figure 6, page 20 shows the single-ended output voltage swing. Figure 7, page 20 shows the peak-to-peak differential output voltage. Consult Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further details. Table 40: GTX_DUAL Tile DC Specifications
Symbol
DVPPIN
DC Parameter
Differential peak-to-peak input voltage Absolute input voltage Common mode input voltage Differential peak-to-peak output voltage (1) Single-ended output voltage swing (1) Common mode output voltage Differential input resistance Differential output resistance Transmitter output skew
Conditions
External AC coupled 4.25 Gb/s External AC coupled > 4.25 Gb/s DC coupled MGTAVTTRX = 1.2V DC coupled MGTAVTTRX = 1.2V TXBUFDIFFCTRL = 111 TXBUFDIFFCTRL = 111 Equation based MGTAVTTTX = 1.2V
Min
200 125 -400
Typ
Max
1800 1800 MGTAVTTRX +400 up to 1320
Units
mV mV mV mV
VIN VCMIN DVPPOUT VSEOUT VCMOUT RIN ROUT TOSKEW CEXT Notes:
1. 2.
800 1400 700 1200 - DVPPOUT/2 85 85 100 100 2 75 100 120 120 8 200
mV mV mV ps nF
Recommended external AC coupling capacitor(2)
The output swing and preemphasis levels are programmable using the attributes discussed in Virtex-5 FPGA RocketIO GTX Transceiver User Guide and can result in values lower than reported in this table. Values outside of this range can be used as appropriate to conform to specific protocols and standards.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
X-Ref Target - Figure 6
+V
P VSEOUT
ds714_06_012109
N 0
Figure 6: Single-Ended Output Voltage Swing
X-Ref Target - Figure 7
+V
0
DVPPOUT DVPPIN
-V
P-N
ds714_07_012109
Figure 7: Peak-to-Peak Differential Output Voltage Table 41 summarizes the DC specifications of the clock input of the GTX_DUAL tile. Figure 8 shows the single-ended input voltage swing. Figure 9 shows the peak-to-peak differential clock input voltage swing. Consult Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further details. Table 41: GTX_DUAL Tile Clock DC Input Level Specification(1)
Symbol
VIDIFF VISE RIN CEXT Notes:
1. VMIN = 0V and VMAX = 1200 mV
DC Parameter
Differential peak-to-peak input voltage Single-ended input voltage Differential input resistance Required external AC coupling capacitor
Conditions
Min
210 105 90
Typ
800 400 105 100
Max
2000 750 130
Units
mV mV nF
X-Ref Target - Figure 8
+V
P
VISE
N
0
Figure 8: Single-Ended Clock Input Voltage Swing Peak-to-Peak
X-Ref Target - Figure 9
ds714_08_012109
+V
P-N
0
VIDIFF
-V
ds714_09_012109
Figure 9: Differential Clock Input Voltage Swing Peak-to-Peak
DS714 (v2.1) July 23, 2010 Product Specification www.xilinx.com 20
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
GTX_DUAL Tile Switching Characteristics
Consult Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further information. Table 42: GTX_DUAL Tile Performance
Symbol
FGTXMAX FGPLLMAX FGPLLMIN
Description
Maximum GTX transceiver data rate Maximum PLL frequency Minimum PLL frequency
Speed Grade -2I
6.5 3.25 1.5
-1I
4.25 3.25 1.5
-1M
4.25 3.25 1.5
Units
Gb/s GHz GHz
Table 43: Dynamic Reconfiguration Port (DRP) in the GTX_DUAL Tile Switching Characteristics
Symbol
FGTXDRPCLK
Description
GTXDRPCLK maximum frequency
Speed Grade -2I
175
-1I
150
-1M
150
Units
MHz
Table 44: GTX_DUAL Tile Reference Clock Switching Characteristics
Symbol
FGCLK TRCLK TFCLK TDCREF TGJTT TLOCK TPHASE Notes:
1. 2. 3. GREFCLK can be used for serial bit rates up to 1 Gb/s; however, Jitter Specifications are not guaranteed when using GREFCLK. GTX_DUAL jitter characteristics measured using a clock with specification TGJTT. A reference clock with higher phase noise can be used with link margin trade off. The selection of the reference clock is application dependent. This parameter describes the quality of the reference clock used during transceiver jitter characterization - see Table 46, page 22 and Table 47, page 23.
Description
Reference clock frequency range(1) Reference clock rise time Reference clock fall time Reference clock duty cycle Reference clock total jitter(2, 3) Clock recovery frequency acquisition time Clock recovery phase acquisition time CLK
Conditions
All Speed Grades Min
60 200 200 40 50 -145 -150 0.25 1 200 60
Typ
Max
650
Units
MHz ps ps % dBc/Hz dBc/Hz ms s
20% - 80% 80% - 20% CLK At 100 KHz At 1 MHz Initial PLL lock Lock to data after PLL has locked to the reference clock
X-Ref Target - Figure 10
TRCLK
80%
20%
TFCLK
ds714_10_012109
Figure 10: Reference Clock Timing Parameters
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 45: GTX_DUAL Tile User Clock Switching Characteristics
Symbol
FTXOUT FRXREC TRX TRX2
Description
TXOUTCLK maximum frequency RXRECCLK maximum frequency RXUSRCLK maximum frequency RXUSRCLK2 maximum frequency
Conditions
Internal 20-bit datapath Internal 16-bit datapath 2 byte or 4 byte interface 1 byte interface 2 byte interface 4 byte interface
Device
FXT FXT FXT FXT FXT
Speed Grade -2I
325 406.25 406.25 406.25 312.5 390.625 203.125
-1I
212.5 265.625 265.625 265.625 235.625 265.625 132.813 265.625 235.625 265.625 132.813
-1M
212.5 265.625 265.625 265.625 235.625 265.625 132.813 265.625 235.625 265.625 132.813
Units
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
TTX TTX2
TXUSRCLK maximum frequency TXUSRCLK2 maximum frequency
2 byte or 4 byte interface 1 byte interface 2 byte interface 4 byte interface
FXT FXT
406.25 312.5 390.625 203.125
Table 46: GTX_DUAL Tile Transmitter Switching Characteristics
Symbol
FGTXTX TRTX TFTX TLLSKEW VTXOOBVDPP TTXOOBTRANSITION TJ6.5 DJ6.5 TJ5.0 DJ5.0 TJ4.25 DJ4.25 TJ3.75 DJ3.75 TJ3.2 DJ3.2 TJ3.2L DJ3.2L TJ2.5 DJ2.5 TJ1.25 DJ1.25 TJ750 DJ750 TJ150 DJ150 Notes:
1. 2. 3. 4. 5. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTX_DUAL sites. Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. These values are NOT intended for protocol specific compliance determinations. PLL frequency at 1.6 GHz and OUTDIV = 1. GREFCLK can be used for serial data rates up to 1.0 Gb/s, but performance is not guaranteed. M-temperature only (0.33 UI for I-temperature)
Description
Serial data rate range TX Rise time TX Fall time TX lane-to-lane skew(1) Electrical idle amplitude Electrical idle transition time Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2) Deterministic Jitter(2) Total Jitter(2, 4) Deterministic Jitter(2, 4) Total Jitter(2, 4) Deterministic Jitter(2, 4)
Condition
20%-80% 80%-20%
Min
0.15
Typ
120 120
Max
FGTXMAX
350 15 75 0.33 0.17 0.33 0.15 0.35(5) 0.14 0.34 0.16 0.20 0.10 0.36 0.16 0.20 0.08 0.15 0.06 0.10 0.03 0.02 0.01
6.5 Gb/s 5.0 Gb/s 4.25 Gb/s 3.75 Gb/s 3.2 Gb/s 3.2 Gb/s(3) 2.5 Gb/s 1.25 Gb/s 750 Mb/s 150 Mb/s
Units Gb/s ps ps ps mV ns UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 47: GTX_DUAL Tile Receiver Switching Characteristics
Symbol
FGTXRX Serial data rate TIme for RXELECIDLE to respond to loss or restoration of data OOB detect threshold peak-to-peak Receiver spread-spectrum tracking(1) Run length (CID) Data/REFCLK PPM offset tolerance
Description
RX oversampler not enabled RX oversampler enabled OOBDETECT_THRESHOLD = 110
Min
0.75 0.15
Typ
Max
FGTXMAX 0.75 75
Units
Gb/s Gb/s ns
TRXELECIDLE RXOOBVDPP RXSST RXRL RXPPMTOL
OOBDETECT_THRESHOLD = 110 Modulated @ 33 KHz Internal AC capacitor bypassed CDR CDR 2nd-order 2nd-order loop disabled loop enabled
55 -5000
135 0 512
mV ppm UI ppm ppm
-200 -2000
200 2000
SJ Jitter
JT_SJ6.5 JT_SJ5.0
Tolerance(2)
Sinusoidal Jitter(3) Sinusoidal Sinusoidal Sinusoidal Sinusoidal Sinusoidal Sinusoidal Sinusoidal Sinusoidal Sinusoidal Jitter(3) Jitter(3) Jitter(3) Jitter(3) Jitter(3) Jitter(3) Jitter(3) Jitter(3, 5) Jitter(3, 5) 6.5 Gb/s 5.0 Gb/s 4.25 Gb/s 3.75 Gb/s 3.2 Gb/s 3.2 Gb/s(4) 0.44 0.44 0.44 0.44 0.45 0.45 0.50 0.50 0.57 0.57 UI UI UI UI UI UI UI UI UI UI
JT_SJ4.25 JT_SJ3.75 JT_SJ3.2 JT_SJ3.2L JT_SJ2.5 JT_SJ1.25 JT_SJ750 JT_SJ150
2.5 Gb/s 1.25 Gb/s 750 Mb/s 150 Mb/s
SJ Jitter Tolerance with Stressed
JT_TJSE4.25 JT_SJSE4.25 Notes:
1. 2. 3. 4. 5. 6.
Eye(2)
4.25 Gb/s 4.25 Gb/s 0.69 0.1 UI UI
Total Jitter with Stressed Eye(6) Sinusoidal Jitter with Stressed Eye(6)
Using PLL_RXDIVSEL_OUT = 1, 2, and 4. All jitter values are based on a Bit Error Ratio of 1e-12. Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter. PLL frequency at 1.6 GHz and OUTDIV = 1. GREFCLK can be used for serial data rates up to 1.0 Gb/s, but performance is not guaranteed. Composite jitter with RX equalizer enabled. DFE disabled.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
CRC Block Switching Characteristics
Table 48: CRC Block Switching Characteristics
Symbol
FCRC
Description
CRCCLK maximum frequency
Speed Grade -2I
325
-1I
270
-1M
270
Units
MHz
Ethernet MAC Switching Characteristics
Consult Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide for further information. Table 49: Maximum Ethernet MAC Performance
Symbol
FTEMACCLIENT
Description
Client interface maximum frequency
Conditions
10 Mb/s - 8-bit width 100 Mb/s - 8-bit width 1000 Mb/s - 8-bit width 2000 Mb/s - 16-bit width
Speed Grade -2I
1.25 12.5 125 125 2.5 25 125 250
-1I
1.25 12.5 125 125 2.5 25 125 250
-1M
1.25 12.5 125 125 2.5 25 125 250
Units
MHz MHz MHz MHz MHz MHz MHz MHz
FTEMACPHY
Physical interface maximum frequency
10 Mb/s - 4-bit width 100 Mb/s - 4-bit width 1000 Mb/s - 8-bit width 2000 Mb/s - 8-bit width
Endpoint Block for PCI Express Designs Switching Characteristics
Consult Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs User Guide for further information. Table 50: Maximum Performance for PCI Express Designs
Symbol
FPCIECORE FPCIEUSER
Description
Core clock maximum frequency User clock maximum frequency
Speed Grade -2I
250 250
-1I
250 250
-1M
250 250
Units
MHz MHz
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
System Monitor Analog-to-Digital Converter Specification
Table 51: Analog-to-Digital Specifications
Parameter Symbol Comments/Conditions Min Typ Max Units
AVDD = 2.5V 2%, VREFP = 2.5V, VREFN = 0V, ADCCLK = 5.2 MHz, TA = TMIN to TMAX, Typical values at TA=+25C DC Accuracy: All external input channels such as VP/VN and VAUXP[15:0]/VAUXN[15:0], Unipolar Mode, and Common Mode = 0V Resolution Integral Nonlinearity Differential Nonlinearity Unipolar Offset Error(1) Bipolar Offset Gain Error(1) Bipolar Gain Error(1) Error(1) INL DNL No missing codes (TMIN to TMAX) Guaranteed Monotonic Uncalibrated Uncalibrated measured in bipolar mode Uncalibrated, Tj = -40C to 100C Uncalibrated, Tj = -55C to 125C Uncalibrated measured in bipolar mode, Tj = -40C to 100C Uncalibrated measured in bipolar mode, Tj = -55C to 125C Total Unadjusted Error (Uncalibrated) Total Unadjusted Error (Calibrated) Calibrated Gain Temperature Coefficient DC Common-Mode Reject CMRRDC TUE TUE Deviation from ideal transfer function. VREFP - VREFN = 2.5V Deviation from ideal transfer function. VREFP - VREFN = 2.5V Variation of FS code with temperature VN = VCM = 0.5V 0.5V, VP - VN = 100mV Number of CLK cycles Number of CLK cycles Number of CLK cycles DRP clock frequency Derived from DCLK, Tj = -40C to 100C Derived from DCLK, Tj = -55C to 125C CLK Duty cycle 4 8 1 2.5 40 Unipolar Operation Differential Inputs Unipolar Common Mode Range (FS input) Differential Common Mode Range (FS input) Bandwidth Auxiliary Analog Inputs Input Voltage Range VAUXP[0] /VAUXN[0] to VAUXP[15] /VAUXN[15] Unipolar Operation Differential Operation Unipolar Common Mode Range (FS input) Differential Common Mode Range (FS input) Bandwidth Input Leakage Current Input Capacitance On-chip Supply Monitor Error VCCINT and VCCAUX with calibration enabled A/D not converting, ADCCLK stopped 0 -0.25 0 +0.3 10 1.0 10 1.0 0 -0.25 0 +0.3 20 1 +0.25 +0.5 +0.7 kHz A pF %
Reading
10 2 0.9 2 2 0.2 0.2 0.2 0.2 10 1 0.01 70 2 30 30 2.0 2.5 2.0 2.5
Bits LSBs LSBs LSBs LSBs % % % % LSBs LSBs LSB/ C dB
Conversion Rate(2)
Conversion Time - Continuous Conversion Time - Event T/H Acquisition Time DRP Clock Frequency ADC Clock Frequency tCONV tCONV tACQ DCLK ADCCLK 26 32 21 250 5.2 5.2 60 1 +0.25 +0.5 +0.7 MHz Volts MHz MHz MHz % V
Analog Inputs(3)
Dedicated Analog Inputs Input Voltage Range VP - VN
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 51: Analog-to-Digital Specifications (Cont'd)
Parameter
On-chip Temperature Monitor Error
Symbol
Comments/Conditions
-40C to +125C with calibration enabled
Min
Typ
Max
4
Units
C
External Reference Inputs(4)
Positive Reference Input Voltage VREFP Range Negative Reference Input Voltage Range Input current VREFN IREF AVDD AIDD Measured Relative to VREFN Measured Relative to AGND ADCCLK = 5.2 MHz Measured Relative to AVSS ADCCLK = 5.2 MHz 2.45 5 2.5 2.45 -50 2.5 0 2.55 100 100 2.55 13 Volts mV A V mA
Power Requirements
Analog Power Supply Analog Supply Current Notes:
1. 2. 3. 4. Offset and gain errors are removed by enabling the System Monitor automatic gain calibration feature. See Virtex-5 FPGA System Monitor User Guide. See "System Monitor Timing" in Virtex-5 FPGA System Monitor User Guide. See "Analog Inputs" in Virtex-5 FPGA System Monitor User Guide for a detailed description. Any variation in the reference voltage from the nominal VREFP = 2.5V and VREFN = 0V will result is a deviation from the ideal transfer function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing the supply voltage and reference to vary by 2% is permitted.
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in Virtex-5Q devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as the Switching Characteristics. Table 52 shows internal (register-to-register) performance. Table 52: Register-to-Register Performance
Register-to-Register (with I/O Delays) Speed Grade -1I
450 450 407 428 428 450 447 323 450 450 450 333 400 450 450 450
Description -2I Basic Functions 16:1 Multiplexer 32:1 Multiplexer 64:1 Multiplexer 9 x 9 Logic Multiplier with 4 pipestages 9 x 9 Logic Multiplier with 5 pipestages 16-bit Adder 32-bit Adder 64-bit Adder Register to LUT to Register 16-bit Counter 32-bit Counter 64-bit Counter Memory Cascaded block RAM (64K) Block RAM Pipelined Single-Port 512 x 36 bits Single-Port 4096 x 4 bits Dual-Port A: 4096 x 4 bits and B: 1024 x 18 bits
500 500 467 438 500 500 500 377 500 500 500 381 450 500 500 500
Units -1M
450 450 407 428 428 450 447 323 450 450 450 333 400 450 450 450 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 52: Register-to-Register Performance (Cont'd)
Register-to-Register (with I/O Delays) Description -2I Distributed RAM Single-Port 16 x 8 Single-Port 32 x 8 Single-Port 64 x 8 Dual-Port 16 x 8 Shift Register Chain 16-bit 32-bit 64-bit Dedicated Arithmetic Logic DSP48E Quad 12-bit Adder/Subtracter DSP48E Dual 24-bit Adder/Subtracter DSP48E 48-bit Adder/Subtracter DSP48E 48-bit Counter DSP48E 48-bit Comparator DSP48E 25 x 18 bit Pipelined Multiplier DSP48E Direct 4-tap FIR Filter Pipelined DSP48E Systolic n-tap FIR Filter Pipelined
Notes:
1. Device used is the XQ5VLX50T- FF1136.
Speed Grade -1I
450 450 450
Units -1M
450 450 450 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
500 500 500
500 500 500 500 500 500 500 500 500 458 500
450 450 438 450 450 450 450 450 450 397 450
450 450 438 450 450 450 450 450 450 397 450
Table 53: Interface Performances
Description Networking Applications SFI-4.1 (SDR LVDS Interface)(1) SPI-4.2 (DDR LVDS Memory Interfaces DDR(3) DDR2(4) QDR II SRAM(5) II(6) 200 MHz 300 MHz 300 MHz 300 MHz 200 MHz 267 MHz 250 MHz 250 MHz 200 MHz 267 MHz 250 MHz 250 MHz Interface)(2) 710 MHz 1.25 Gb/s 645 MHz 1.0 Gb/s 645 MHz 1.0 Gb/s Speed Grade -2I -1I
-1M
RLDRAM
Notes: Performance defined using design implementation described in application note XAPP856, SFI-4.1 16-Channel SDR Interface with Bus Alignment. 2. Performance defined using design implementation described in application note XAPP860, 16-Channel, DDR LVDS Interface with Real-time Window Monitoring. 3. Performance defined using design implementation described in application note XAPP851, DDR SDRAM Controller. 4. Performance defined using design implementation described in application note XAPP858, High-Performance DDR2 SDRAM Interface Data Capture. 5. Performance defined using design implementation described in application note XAPP853, QDRII SRAM Interface. 6. Performance defined using design implementation described in application note XAPP852, Synthesizable RLDRAM II Controller.
1.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Switching Characteristics
All values represented in this data sheet are based on speed specification version 1.71. Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: Advance These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some underreporting might still occur. Preliminary These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Production These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. All specifications are always representative of worst-case supply voltage and junction temperature conditions. Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 54 correlates the current status of each Virtex-5Q device on a per speed grade basis. Table 54: Virtex-5Q Device Speed Grade Designations
Device
XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T
Speed Grade Designations Advance Preliminary Production
-2I, -1I -2I, -1I -2I, -1I -2I, -1I -2I, -1I -2I, -1I -1I -2I, -1I -2I, -1I -1I -2I, -1I, -1M -2I, -1I, -1M -2I, -1I -1I
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex-5Q devices.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Production Silicon and ISE Software Status
In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases. Table 55 lists the production released Virtex-5Q family member, speed grade, and the minimum corresponding supported speed specification version and ISE(R) software revisions. The ISE software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid. Table 55: Virtex-5Q Device Production Software(1) and Speed Specification Release
Device
XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T Notes:
1. 2. Listed software revisions are those for production-released Virtex-5Q family members. Blank entries indicate a device and/or speed grade in advance or preliminary status.
Speed Grade Designations -2I -1I -1M
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A ISE 12.2 v1.71 ISE 12.2 v1.71 N/A N/A
ISE 11.2 v1.65 ISE 11.2 v1.65 ISE 11.2 v1.65 ISE 11.2 v1.65 ISE 11.2 v1.65 ISE 12.2 v1.71 ISE 11.2 v1.65 N/A ISE 11.2 v1.65
ISE 11.2 v1.65 ISE 12.2 v1.71 ISE 11.2 v1.65 N/A ISE 11.2 v1.65
ISE 11.2 v1.65 ISE 11.2 v1.65 ISE 11.2 v1.65 N/A ISE 11.2 v1.65
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
IOB Pad Input/Output/3-State Switching Characteristics
Table 56 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer. TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer. Table 56: IOB Switching Characteristics
TIOPI I/O Standard -2(I)
LVDS_25 LVDSEXT_25 HT_25 BLVDS_25 RSDS_25 (point to point) ULVDS_25 PCI33_3 PCI66_3 PCI-X GTL GTLP HSTL_I HSTL_II HSTL_III HSTL_IV HSTL_I _18 HSTL_II _18 HSTL_III _18 HSTL_IV_18 SSTL2_I SSTL2_II LVTTL, Slow, 2 mA LVTTL, Slow, 4 mA LVTTL, Slow, 6 mA LVTTL, Slow, 8 mA LVTTL, Slow, 12 mA LVTTL, Slow, 16 mA LVTTL, Slow, 24 mA 0.90 1.16 0.90 0.90 0.90 0.90 0.70 0.70 0.70 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.70 0.70 0.70 0.70 0.70 0.70 0.70
TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. Table 57, page 34 summarizes the value of TIOTPHZ. TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state).
TIOOP Speed Grade -1(M)
1.11 1.36 1.11 1.12 1.11 1.11 1.05 1.05 1.05 1.11 1.05 1.07 1.05 1.40 1.40 1.26 1.13 1.45 1.45 1.11 1.11 1.02 1.02 1.02 1.02 1.02 1.02 1.02
TIOTP Speed Grade -1(M)
1.79 1.82 1.79 1.91 1.79 1.79 2.41 2.41 2.03 2.10 2.14 1.96 1.84 2.03 2.07 1.91 1.79 1.98 1.92 1.94 1.83 6.05 4.13 3.91 2.91 2.56 2.47 2.48
Speed Grade -1(I)
1.06 1.30 1.06 1.06 1.06 1.06 0.82 0.82 0.82 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 0.82 0.82 0.82 0.82 0.82 0.82 0.82
Units -1(M)
1.79 1.82 1.79 1.91 1.79 1.79 2.41 2.41 2.03 2.10 2.14 1.96 1.84 2.03 2.07 1.91 1.79 1.98 1.92 1.94 1.83 6.05 4.13 3.91 2.91 2.56 2.47 2.48 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-2(I)
1.29 1.34 1.26 1.38 1.29 1.27 2.06 2.06 1.56 1.63 1.68 1.57 1.53 1.60 1.60 1.55 1.51 1.61 1.57 1.64 1.55 4.47 3.09 2.91 2.30 2.15 2.04 2.07
-1(I)
1.44 1.49 1.40 1.58 1.44 1.41 2.38 2.38 1.80 1.86 1.93 1.79 1.74 1.85 1.83 1.77 1.72 1.85 1.81 1.78 1.76 5.01 3.41 3.29 2.61 2.46 2.34 2.38
-2(I)
1.29 1.34 1.26 1.38 1.29 1.27 2.06 2.06 1.56 1.63 1.68 1.57 1.53 1.60 1.60 1.55 1.51 1.61 1.57 1.64 1.55 4.47 3.09 2.91 2.30 2.15 2.04 2.07
-1(I)
1.44 1.49 1.40 1.58 1.44 1.41 2.38 2.38 1.80 1.86 1.93 1.79 1.74 1.85 1.83 1.77 1.72 1.85 1.81 1.78 1.76 5.01 3.41 3.29 2.61 2.46 2.34 2.38
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 56: IOB Switching Characteristics (Cont'd)
TIOPI I/O Standard -2(I)
LVTTL, Fast, 2 mA LVTTL, Fast, 4 mA LVTTL, Fast, 6 mA LVTTL, Fast, 8 mA LVTTL, Fast, 12 mA LVTTL, Fast, 16 mA LVTTL, Fast, 24 mA LVCMOS33, Slow, 2 mA LVCMOS33, Slow, 4 mA LVCMOS33, Slow, 6 mA LVCMOS33, Slow, 8 mA LVCMOS33, Slow, 12 mA LVCMOS33, Slow, 16 mA LVCMOS33, Slow, 24 mA LVCMOS33, Fast, 2 mA LVCMOS33, Fast, 4 mA LVCMOS33, Fast, 6 mA LVCMOS33, Fast, 8 mA LVCMOS33, Fast, 12 mA LVCMOS33, Fast, 16 mA LVCMOS33, Fast, 24 mA LVCMOS25, Slow, 2 mA LVCMOS25, Slow, 4 mA LVCMOS25, Slow, 6 mA LVCMOS25, Slow, 8 mA LVCMOS25, Slow, 12 mA LVCMOS25, Slow, 16 mA LVCMOS25, Slow, 24 mA LVCMOS25, Fast, 2 mA LVCMOS25, Fast, 4 mA LVCMOS25, Fast, 6 mA LVCMOS25, Fast, 8 mA LVCMOS25, Fast, 12 mA LVCMOS25, Fast, 16 mA LVCMOS25, Fast, 24 mA LVCMOS18, Slow, 2 mA LVCMOS18, Slow, 4 mA LVCMOS18, Slow, 6 mA LVCMOS18, Slow, 8 mA 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.76 0.76 0.76 0.76
TIOOP Speed Grade -1(M)
1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 1.14 1.14 1.14 1.14
TIOTP Speed Grade -1(M)
5.58 3.72 3.34 2.39 2.31 2.27 2.27 6.05 4.13 3.89 2.91 2.56 2.44 2.48 5.56 3.70 3.32 2.35 2.31 2.28 2.26 5.06 3.71 3.42 2.93 2.73 2.31 2.37 4.48 3.23 2.89 2.38 1.94 1.99 1.98 6.81 4.30 3.76 3.32
Speed Grade -1(I)
0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.89 0.89 0.89 0.89
Units -1(M)
5.58 3.72 3.34 2.39 2.31 2.27 2.27 6.05 4.13 3.89 2.91 2.56 2.44 2.48 5.56 3.70 3.32 2.35 2.31 2.28 2.26 5.06 3.71 3.42 2.93 2.73 2.31 2.37 4.48 3.23 2.89 2.38 1.94 1.99 1.98 6.81 4.30 3.76 3.32 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-2(I)
3.61 2.55 2.31 1.82 1.63 1.57 1.52 3.96 3.09 2.86 2.26 2.14 2.04 2.07 3.20 2.50 2.27 1.79 1.61 1.56 1.51 3.97 2.60 2.41 2.26 2.31 2.02 2.04 3.41 2.08 1.92 1.83 1.69 1.60 1.54 4.56 3.32 2.61 2.37
-1(I)
4.05 2.90 2.63 2.09 1.89 1.81 1.74 4.44 3.49 3.24 2.57 2.42 2.31 2.35 3.59 2.84 2.59 2.05 1.86 1.80 1.74 4.42 2.94 2.74 2.56 2.63 2.30 2.34 3.82 2.37 2.20 2.09 1.94 1.85 1.76 5.09 3.75 2.97 2.69
-2(I)
3.61 2.55 2.31 1.82 1.63 1.57 1.52 3.96 3.09 2.86 2.26 2.14 2.04 2.07 3.20 2.50 2.27 1.79 1.61 1.56 1.51 3.97 2.60 2.41 2.26 2.31 2.02 2.04 3.41 2.08 1.92 1.83 1.69 1.60 1.54 4.56 3.32 2.61 2.37
-1(I)
4.05 2.90 2.63 2.09 1.89 1.81 1.74 4.44 3.49 3.24 2.57 2.42 2.31 2.35 3.59 2.84 2.59 2.05 1.86 1.80 1.74 4.42 2.94 2.74 2.56 2.63 2.30 2.34 3.82 2.37 2.20 2.09 1.94 1.85 1.76 5.09 3.75 2.97 2.69
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 56: IOB Switching Characteristics (Cont'd)
TIOPI I/O Standard -2(I)
LVCMOS18, Slow, 12 mA LVCMOS18, Slow, 16 mA LVCMOS18, Fast, 2 mA LVCMOS18, Fast, 4 mA LVCMOS18, Fast, 6 mA LVCMOS18, Fast, 8 mA LVCMOS18, Fast, 12 mA LVCMOS18, Fast, 16 mA LVCMOS15, Slow, 2 mA LVCMOS15, Slow, 4 mA LVCMOS15, Slow, 6 mA LVCMOS15, Slow, 8 mA LVCMOS15, Slow, 12 mA LVCMOS15, Slow, 16 mA LVCMOS15, Fast, 2 mA LVCMOS15, Fast, 4 mA LVCMOS15, Fast, 6 mA LVCMOS15, Fast, 8 mA LVCMOS15, Fast, 12 mA LVCMOS15, Fast, 16 mA LVCMOS12, Slow, 2 mA LVCMOS12, Slow, 4 mA LVCMOS12, Slow, 6 mA LVCMOS12, Slow, 8 mA LVCMOS12, Fast, 2 mA LVCMOS12, Fast, 4 mA LVCMOS12, Fast, 6 mA LVCMOS12, Fast, 8 mA LVDCI_33 LVDCI_25 LVDCI_18 LVDCI_15 LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2_15 GTL_DCI GTLP_DCI LVPECL_25 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.83 0.83 0.83 0.83 0.83 0.83 0.83 0.83 0.83 0.83 0.83 0.83 0.96 0.96 0.96 0.96 0.96 0.96 0.96 0.96 0.70 0.70 0.76 0.83 0.70 0.76 0.83 0.85 0.85 0.90
TIOOP Speed Grade -1(M)
1.14 1.14 1.14 1.14 1.14 1.14 1.14 1.14 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.61 1.61 1.61 1.61 1.61 1.61 1.61 1.61 1.02 0.82 1.14 1.23 0.82 1.14 1.23 1.11 1.05 1.12
TIOTP Speed Grade -1(M)
2.59 2.53 6.23 3.80 3.30 2.66 2.07 1.97 5.08 3.48 2.55 2.46 2.28 2.23 4.99 3.39 2.41 2.26 1.99 1.92 5.58 3.13 2.54 2.51 5.54 3.01 2.44 2.28 2.66 2.65 2.85 2.74 2.12 2.16 2.33 1.79 1.94 1.91
Speed Grade -1(I)
0.89 0.89 0.89 0.89 0.89 0.89 0.89 0.89 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 1.14 1.14 1.14 1.14 1.14 1.14 1.14 1.14 0.82 0.82 0.89 0.98 0.82 0.89 0.98 1.00 1.00 1.06
Units -1(M)
2.59 2.53 6.23 3.80 3.30 2.66 2.07 1.97 5.08 3.48 2.55 2.46 2.28 2.23 4.99 3.39 2.41 2.26 1.99 1.92 5.58 3.13 2.54 2.51 5.54 3.01 2.44 2.28 2.66 2.65 2.85 2.74 2.12 2.16 2.33 1.79 1.94 1.91 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-2(I)
2.16 2.14 3.71 2.61 2.06 1.87 1.68 1.61 3.84 2.40 2.20 2.12 1.95 1.91 3.07 1.95 1.80 1.74 1.60 1.53 3.98 2.33 2.18 2.14 3.38 1.91 1.78 1.70 1.66 1.71 1.78 1.75 1.51 1.60 1.65 1.47 1.52 1.42
-1(I)
2.47 2.45 4.16 2.98 2.35 2.13 1.93 1.86 4.34 2.74 2.52 2.43 2.25 2.20 3.48 2.23 2.06 2.00 1.86 1.77 4.58 2.66 2.45 2.48 3.87 2.20 2.08 1.97 1.90 1.93 1.99 2.02 1.74 1.85 1.91 1.65 1.76 1.62
-2(I)
2.16 2.14 3.71 2.61 2.06 1.87 1.68 1.61 3.84 2.40 2.20 2.12 1.95 1.91 3.07 1.95 1.80 1.74 1.60 1.53 3.98 2.33 2.18 2.14 3.38 1.91 1.78 1.70 1.66 1.71 1.78 1.75 1.51 1.60 1.65 1.47 1.52 1.42
-1(I)
2.47 2.45 4.16 2.98 2.35 2.13 1.93 1.86 4.34 2.74 2.52 2.43 2.25 2.20 3.48 2.23 2.06 2.00 1.86 1.77 4.58 2.66 2.45 2.48 3.87 2.20 2.08 1.97 1.90 1.93 1.99 2.02 1.74 1.85 1.91 1.65 1.76 1.62
DS714 (v2.1) July 23, 2010 Product Specification
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 56: IOB Switching Characteristics (Cont'd)
TIOPI I/O Standard -2(I)
HSTL_I_12 HSTL_I_DCI HSTL_II_DCI HSTL_II_T_DCI HSTL_III_DCI HSTL_IV_DCI HSTL_I_DCI_18 HSTL_II_DCI_18 HSTL_II _T_DCI_18 HSTL_III_DCI_18 HSTL_IV_DCI_18 DIFF_HSTL_I_18 DIFF_HSTL_I_DCI_18 DIFF_HSTL_I DIFF_HSTL_I_DCI DIFF_HSTL_II_18 DIFF_HSTL_II_DCI_18 DIFF_HSTL_II DIFF_HSTL_II_DCI SSTL2_I_DCI SSTL2_II_DCI SSTL2_II_T_DCI SSTL18_I SSTL18_II SSTL18_I_DCI SSTL18_II_DCI SSTL18_II_T_DCI DIFF_SSTL2_I DIFF_SSTL2_I_DCI DIFF_SSTL18_I DIFF_SSTL18_I_DCI DIFF_SSTL2_II DIFF_SSTL2_II_DCI DIFF_SSTL18_II DIFF_SSTL18_II_DCI Notes:
1. M-temperature IOB delays are slightly larger than timing analyzer/speeds specification values. Correct values are listed in this table. It is necessary to allow for this difference in the design.
TIOOP Speed Grade -1(M)
1.08 1.07 1.05 1.05 1.40 1.40 1.26 1.13 1.13 1.45 1.45 1.10 1.10 1.10 1.10 1.10 1.10 1.10 1.10 1.11 1.11 1.11 1.08 1.08 1.08 1.08 1.08 1.11 1.11 1.10 1.10 1.11 1.11 1.10 1.10
TIOTP Speed Grade -1(M)
1.98 1.98 1.86 1.98 2.27 1.84 1.95 1.77 1.95 2.16 1.84 1.91 1.91 1.91 1.95 1.91 1.91 1.91 1.91 3.30 1.97 3.30 1.94 1.81 1.97 1.86 1.97 1.97 1.94 1.94 1.94 1.91 1.90 1.91 1.91
Speed Grade -1(I)
1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06
Units -1(M)
1.98 1.98 1.86 1.98 2.27 1.84 1.95 1.77 1.95 2.16 1.84 1.91 1.91 1.91 1.95 1.91 1.91 1.91 1.91 3.30 1.97 3.30 1.94 1.81 1.97 1.86 1.97 1.97 1.94 1.94 1.94 1.91 1.90 1.91 1.91 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-2(I)
1.61 1.56 1.48 1.56 1.72 1.46 1.50 1.43 1.50 1.69 1.44 1.55 1.50 1.57 1.56 1.51 1.43 1.53 1.48 1.56 1.48 1.56 1.61 1.53 1.53 1.44 1.53 1.64 1.56 1.61 1.53 1.55 1.48 1.53 1.44
-1(I)
1.85 1.77 1.69 1.77 1.95 1.64 1.70 1.64 1.70 1.91 1.62 1.77 1.70 1.79 1.77 1.72 1.64 1.74 1.69 1.78 1.70 1.78 1.84 1.75 1.74 1.64 1.74 1.87 1.78 1.84 1.74 1.76 1.70 1.75 1.64
-2(I)
1.61 1.56 1.48 1.56 1.72 1.46 1.50 1.43 1.50 1.69 1.44 1.55 1.50 1.57 1.56 1.51 1.43 1.53 1.48 1.56 1.48 1.56 1.61 1.53 1.53 1.44 1.53 1.64 1.56 1.61 1.53 1.55 1.48 1.53 1.44
-1(I)
1.85 1.77 1.69 1.77 1.95 1.64 1.70 1.64 1.70 1.91 1.62 1.77 1.70 1.79 1.77 1.72 1.64 1.74 1.69 1.78 1.70 1.78 1.84 1.75 1.74 1.64 1.74 1.87 1.78 1.84 1.74 1.76 1.70 1.75 1.64
0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.90 0.90 0.90 0.90 0.90 0.90 0.90 0.90 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.90 0.90 0.90 0.90 0.90 0.90 0.90 0.90
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 57: IOB 3-state ON Output Switching Characteristics (TIOTPHZ)
Symbol
TIOTPHZ
Description
T input to Pad high-impedance
Speed Grade -2I
1.01
-1I
1.12
-1M
1.12
Units
ns
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 58 shows the test setup parameters used for measuring input delay. Table 58: Input Delay Measurement Methodology
Description
LVTTL (Low-Voltage Transistor-Transistor Logic) LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, 1.5V LVCMOS, 1.2V PCI (Peripheral Component Interconnect), 33 MHz, 3.3V PCI, 66 MHz, 3.3V PCI-X, 133 MHz, 3.3V GTL (Gunning Transceiver Logic) GTL Plus
I/O Standard Attribute
LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33_3 PCI66_3 PCIX GTL GTLP
VL (1, 2)
0 0 0 0 0 0
VH (1, 2)
3.0 3.3 2.5 1.8 1.5 1.2
VMEAS
(1, 4, 5)
VREF (1, 3, 5)
- - - - - - - - -
1.4 1.65 1.25 0.9 0.75 0.6
Per PCITM Specification Per PCI Specification Per PCI-XTM Specification VREF - 0.2 VREF - 0.2 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 1.00 VREF - 0.75 VREF - 0.5 VREF - (0.2 xVCCO) 1.2 - 0.125 1.2 - 0.125 0.6 - 0.125 1.15 - 0.3 VREF + 0.2 VREF + 0.2 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 1.00 VREF + 0.75 VREF + 0.5 VREF + (0.2 xVCCO) 1.2 + 0.125 1.2 + 0.125 0.6 + 0.125 1.15 - 0.3 VREF VREF VREF VREF VREF VREF VREF VREF VREF VREF 0(6) 0(6) 0(6) 0(6)
0.80 1.0 0.75 0.90 0.90 1.08 1.5 1.25 0.90 AGP Spec
HSTL (High-Speed Transceiver Logic), Class I & II HSTL_I, HSTL_II HSTL, Class III & IV HSTL_III, HSTL_IV HSTL, Class I & II, 1.8V HSTL, Class III & IV, 1.8V SSTL (Stub Terminated Transceiver Logic), Class I & II, 3.3V SSTL, Class I & II, 2.5V SSTL, Class I & II, 1.8V AGP-2X/AGP (Accelerated Graphics Port) LVDS (Low-Voltage Differential Signaling), 2.5V LVDSEXT (LVDS Extended Mode), 2.5V LDT (HyperTransport), 2.5V LVPECL (Low-Voltage Positive Emitter-Coupled Logic), 2.5V Notes:
1.
HSTL_I_18, HSTL_II_18 HSTL_III_18, HSTL_IV_18 SSTL3_I, SSTL3_II SSTL2_I, SSTL2_II SSTL18_I, SSTL18_II AGP LVDS_25 LVDSEXT_25 LDT_25 LVPECL_25
2. 3. 4. 5. 6.
The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other DCI standards are the same for the corresponding non-DCI standards. Input waveform switches between VL and VH. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical. Input voltage level from which measurement starts. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 11, page 35. The value given is the differential input voltage.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Output Delay Measurements
Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pF) across approximately 4" of FR4 microstrip trace. Standard termination was used for all testing. The propagation delay of the 4" trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in Figure 11 and Figure 12.
X-Ref Target - Figure 11
X-Ref Target - Figure 12
FPGA Output
+ CREF RREF VMEAS -
ds714_12_012109
VREF
Figure 12: Differential Test Setup Measurements and test conditions are reflected in the IBIS models except where the IBIS format precludes it. Parameters VREF , RREF , CREF , and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using the following method: 1. Simulate the output driver of choice into the generalized test setup, using values from Table 59. 2. Record the time to VMEAS .
DS714_11_012109
FPGA Output
RREF
VMEAS
(voltage level when taking delay measurement)
CREF
(probe capacitance)
Figure 11: Single Ended Test Setup
3. Simulate the output driver of choice into the actual PCB trace and load, using the appropriate IBIS model or capacitance value to represent the load. 4. Record the time to VMEAS . 5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the PCB trace.
Table 59: Output Delay Measurement Methodology
Description
LVTTL (Low-Voltage Transistor-Transistor Logic) LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, 1.5V LVCMOS, 1.2V PCI (Peripheral Component Interface), 33 MHz, 3.3V
I/O Standard Attribute
LVTTL (all) LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33_3 (rising edge) PCI33_3 (falling edge) PCI66_3 (rising edge) PCI66_3 (falling edge) PCIX (rising edge) PCIX (falling edge GTL GTLP HSTL_I HSTL_II HSTL_III
RREF ()
1M 1M 1M 1M 1M 1M 25 25 25 25 25 25 25 25 50 25 50
CREF(1) (pF)
0 0 0 0 0 0 10 (2) 10 (2) 10 (2) 10 (2) 10 (3) 10 (3) 0 0 0 0 0
VMEAS (V)
1.4 1.65 1.25 0.9 0.75 0.6 0.94 2.03 0.94 2.03 0.94 2.03 0.8 1.0 VREF VREF 0.9
VREF (V)
0 0 0 0 0 0 0 3.3 0 3.3
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V GTL (Gunning Transceiver Logic) GTL Plus HSTL (High-Speed Transceiver Logic), Class I HSTL, Class II HSTL, Class III
3.3 1.2 1.5 0.75 0.75 1.5
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 59: Output Delay Measurement Methodology (Cont'd)
Description
HSTL, Class IV HSTL, Class I, 1.8V HSTL, Class II, 1.8V HSTL, Class III, 1.8V HSTL, Class IV, 1.8V SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL, Class II, 1.8V SSTL, Class I, 2.5V SSTL, Class II, 2.5V LVDS (Low-Voltage Differential Signaling), 2.5V LVDSEXT (LVDS Extended Mode), 2.5V BLVDS (Bus LVDS), 2.5V LDT (HyperTransport), 2.5V LVPECL (Low-Voltage Positive Emitter-Coupled Logic), 2.5V LVDCI/HSLVDCI (Low-Voltage Digitally Controlled Impedance), 3.3V LVDCI/HSLVDCI, 2.5V LVDCI/HSLVDCI, 1.8V LVDCI/HSLVDCI, 1.5V HSTL_IV HSTL_I_18 HSTL_II_18 HSTL_III_18 HSTL_IV_18 SSTL18_I SSTL18_II SSTL2_I SSTL2_II LVDS_25 LVDS_25 BLVDS_25 LDT_25 LVPECL_25 LVDCI_33, HSLVDCI_33 LVDCI_25, HSLVDCI_25 LVDCI_18, HSLVDCI_18 LVDCI_15, HSLVDCI_15
I/O Standard Attribute
RREF ()
25 50 25 50 25 50 25 50 25 100 100 100 100 100 1M 1M 1M 1M 50 50 50 50 50 50 50 50
CREF(1) (pF)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VMEAS (V)
0.9 VREF VREF 1.1 1.1 VREF VREF VREF VREF 0(4) 0(4) 0(4) 0(4) 0(4) 1.65 1.25 0.9 0.75 VREF 0.9 VREF 1.1 VREF VREF 0.8 1.0
VREF (V)
1.5 0.9 0.9 1.8 1.8 0.9 0.9 1.25 1.25 1.2 1.2 0 0.6 0 0 0 0 0 0.75 1.5 0.9 1.8 0.9 1.25 1.2 1.5
HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI HSTL, Class III & IV, with DCI HSTL, Class I & II, 1.8V, with DCI HSTL, Class III & IV, 1.8V, with DCI HSTL_III_DCI, HSTL_IV_DCI HSTL_I_DCI_18, HSTL_II_DCI_18 HSTL_III_DCI_18, HSTL_IV_DCI_18
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI SSTL, Class I & II, 2.5V, with DCI GTL (Gunning Transceiver Logic) with DCI GTL Plus with DCI Notes:
1. 2. 3. 4. CREF is the capacitance of the probe, nominally 0 pF. Per PCI specifications. Per PCI-X specifications. The value given is the differential input voltage.
SSTL2_I_DCI, SSTL2_II_DCI GTL_DCI GTLP_DCI
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Input/Output Logic Switching Characteristics
Table 60: ILOGIC Switching Characteristics
Symbol Setup/Hold
TICE1CK/TICKCE1 TISRCK/TICKSR TIDOCK/TIOCKD TIDOCKD/TIOCKDD CE1 pin Setup/Hold with respect to CLK SR/REV pin Setup/Hold with respect to CLK D pin Setup/Hold with respect to CLK without Delay DDLY pin Setup/Hold with respect to CLK (using IODELAY) 0.49 -0.24 1.00 -0.20 0.37 -0.12 0.33 -0.09 0.59 -0.24 1.22 -0.20 0.39 -0.12 0.36 -0.08 0.59 -0.17 1.22 -0.22 0.39 -0.12 0.36 -0.08 ns ns ns ns
Description
Speed Grade -2I -1I -1M
Units
Combinatorial
TIDI TIDID D pin to O pin propagation delay, no Delay DDLY pin to O pin propagation delay (using IODELAY) 0.26 0.22 0.30 0.26 0.30 0.26 ns ns
Sequential Delays
TIDLO TIDLOD TICKQ TRQ TGSRQ D pin to Q1 pin using flip-flop as a latch without Delay DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY) CLK to Q outputs SR/REV pin to OQ/TQ out Global Set/Reset to Q outputs 0.50 0.46 0.52 1.28 7.30 0.58 0.55 0.60 1.53 10.10 0.58 0.55 0.60 1.53 10.10 ns ns ns ns ns
Set/Reset
TRPW Minimum Pulse Width, SR/REV inputs 0.95 1.20 1.20 ns, Min
Table 61: OLOGIC Switching Characteristics
Symbol Setup/Hold
TODCK/TOCKD TOOCECK/TOCKOCE TOSRCK/TOCKSR TOTCK/TOCKT TOTCECK/TOCKTCE D1/D2 pins Setup/Hold with respect to CLK OCE pin Setup/Hold with respect to CLK SR/REV pin Setup/Hold with respect to CLK T1/T2 pins Setup/Hold with respect to CLK TCE pin Setup/Hold with respect to CLK 0.36 -0.21 0.19 -0.07 1.02 -0.20 0.34 -0.18 0.23 -0.06 0.44 -0.21 0.23 -0.07 1.16 -0.20 0.41 -0.18 0.29 -0.06 0.44 -0.14 0.23 -0.04 1.16 -0.20 0.41 -0.12 0.29 -0.01 ns ns ns ns ns
Description
Speed Grade -2I -1I -1M
Units
Combinatorial
TDOQ D1 to OQ out or T1 to TQ out 0.70 0.83 0.83 ns
Sequential Delays
TOCKQ TRQ TGSRQ CLK to OQ/TQ out SR/REV pin to OQ/TQ out Global Set/Reset to Q outputs 0.62 1.89 7.30 0.62 2.27 10.10 0.62 2.27 10.10 ns ns ns
Set/Reset
TRPW Minimum Pulse Width, SR/REV inputs 0.98 1.25 1.25 ns, Min
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Input Serializer/Deserializer Switching Characteristics
Table 62: ISERDES Switching Characteristics
Symbol Setup/Hold for Control Lines
TISCCK_BITSLIP/ TISCKC_BITSLIP TISCCK_CE / TISCKC_CE(2) TISCCK_CE2 / TISCKC_CE2(2) BITSLIP pin Setup/Hold with respect to CLKDIV CE pin Setup/Hold with respect to CLK (for CE1) CE pin Setup/Hold with respect to CLKDIV (for CE2) 0.11 0.00 0.49 -0.24 0.04 0.13 0.12 0.00 0.59 -0.24 0.06 0.15 0.12 0.00 0.59 -0.17 0.06 0.15 ns ns ns
Description
Speed Grade -2I -1I -1M
Units
Setup/Hold for Data Lines
TISDCK_D /TISCKD_D TISDCK_DDLY /TISCKD_DDLY TISDCK_DDR /TISCKD_DDR TISDCK_DDLY_DDR TISCKD_DDLY_DDR D pin Setup/Hold with respect to CLK DDLY pin Setup/Hold with respect to CLK (using IODELAY) D pin Setup/Hold with respect to CLK at DDR mode D pin Setup/Hold with respect to CLK at DDR mode (using IODELAY) 0.37 -0.12 0.33 -0.09 0.37 -0.12 0.33 -0.09 0.39 -0.12 0.36 -0.08 0.39 -0.12 0.36 -0.08 0.39 -0.12 0.36 -0.08 0.39 -0.12 0.36 -0.08 ns ns ns ns
Sequential Delays
TISCKO_Q CLKDIV to out at Q pin 0.51 0.60 0.60 ns
Propagation Delays
TISDO_DO Notes:
1. 2. Recorded at 0 tap value. TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in TRACE report.
D input to DO output pin
0.22
0.26
0.26
ns
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Output Serializer/Deserializer Switching Characteristics
Table 63: OSERDES Switching Characteristics
Symbol Setup/Hold
TOSDCK_D/TOSCKD_D TOSDCK_T/TOSCKD_T(1) TOSDCK_T2/TOSCKD_T2(1) TOSCCK_OCE/TOSCKC_OCE TOSCCK_S TOSCCK_TCE/TOSCKC_TCE D input Setup/Hold with respect to CLKDIV T input Setup/Hold with respect to CLK T input Setup/Hold with respect to CLKDIV OCE input Setup/Hold with respect to CLK SR (Reset) input Setup with respect to CLKDIV TCE input Setup/Hold with respect to CLK 0.24 -0.02 0.34 -0.18 0.24 -0.03 0.19 -0.07 0.58 0.23 -0.06 0.30 -0.02 0.41 -0.18 0.28 -0.03 0.23 -0.07 0.70 0.29 -0.06 0.30 -0.02 0.41 -0.12 0.28 -0.03 0.23 -0.04 0.70 0.29 -0.01 ns ns ns ns ns ns
Description
Speed Grade -2I -1I -1M
Units
Sequential Delays
TOSCKO_OQ TOSCKO_TQ Clock to out from CLK to OQ Clock to out from CLK to TQ 0.60 0.62 0.61 0.62 0.61 0.62 ns ns
Combinatorial
TOSDO_TTQ TOSCO_OQ TOSCO_TQ Notes:
1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in TRACE report.
T input to TQ Out Asynchronous Reset to OQ Asynchronous Reset to TQ
0.70 1.82 1.89
0.83 2.19 2.27
0.83 2.19 2.27
ns ns ns
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Input/Output Delay Switching Characteristics
Table 64: Input/Output Delay Switching Characteristics
Symbol
IDELAYCTRL TIDELAYCTRLCO_RDY FIDELAYCTRL_REF TIDELAYCTRL_RPW IODELAY TIDELAYRESOLUTION IODELAY Chain Delay Resolution Pattern dependent period jitter in delay chain for clock pattern Pattern dependent period jitter in delay chain for random data pattern (PRBS 23) Maximum frequency of CLK input to IODELAY CE pin Setup/Hold with respect to CK INC pin Setup/Hold with respect to CK RST pin Setup/Hold with respect to CK TSCONTROL delay to MUXE/MUXF switching and through IODELAY Propagation delay through IODELAY Propagation delay through IODELAY 0 5 250 0.34 -0.06 0.20 0.04 0.28 -0.12 Note 3 Note 3 Note 3 1/(64 x FREF x 1e6)(1) 0 5 250 0.42 -0.06 0.24 0.06 0.33 -0.12 Note 3 Note 3 Note 3 0 5 250 0.42 -0.06 0.24 0.06 0.33 -0.12 Note 3 Note 3 Note 3 ps Note 2 Note 2 MHz ns ns ns Reset to Ready for IDELAYCTRL REFCLK frequency 3.00 200.00 10 50.00 3.00 200.00 10 50.00 3.00 200.00 10 50.00 s MHz MHz ns
Description
Speed Grade -2I -1I -1M
Units
IDELAYCTRL_REF_PRECISION REFCLK precision Minimum Reset pulse width
TIDELAYPAT_JIT
TIODELAY_CLK_MAX TIODCCK_CE / TIODCKC_CE TIODCK_INC/ TIODCKC_INC TIODCK_RST/ TIODCKC_RST TIODDO_T TIODDO_IDATAIN TIODDO_ODATAIN
Notes: 1. Average Tap Delay at 200 MHz = 78 ps. 2. Units in ps, peak-to-peak per tap, in High Performance mode. 3. Delay depends on IODELAY tap setting. See TRACE report for actual values.
CLB Switching Characteristics
Table 65: CLB Switching Characteristics
Symbol Combinatorial Delays
TILO An - Dn LUT address to A An - Dn LUT address to AMUX/CMUX An - Dn LUT address to BMUX_A TITO TAXA TAXB TAXC TAXD TBXB An - Dn inputs to A - D Q outputs AX inputs to AMUX output AX inputs to BMUX output AX inputs to CMUX output AX inputs to DMUX output BX inputs to BMUX output 0.09 0.22 0.35 0.77 0.44 0.52 0.36 0.62 0.41 0.10 0.25 0.40 0.90 0.53 0.61 0.42 0.73 0.48 0.10 0.25 0.40 0.90 0.53 0.61 0.42 0.73 0.48 ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max
Description
Speed Grade -2I -1I -1M
Units
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 65: CLB Switching Characteristics (Cont'd)
Symbol
TBXD TCXB TCXD TDXD TOPCYA TOPCYB TOPCYC TOPCYD TAXCY TBXCY TCXCY TDXCY TBYP TCINA TCINB TCINC TCIND
Description
BX inputs to DMUX output CX inputs to CMUX output CX inputs to DMUX output DX inputs to DMUX output An input to COUT output Bn input to COUT output Cn input to COUT output Dn input to COUT output AX input to COUT output BX input to COUT output CX input to COUT output DX input to COUT output CIN input to COUT output CIN input to AMUX output CIN input to BMUX output CIN input to CMUX output CIN input to DMUX output
Speed Grade -2I
0.51 0.36 0.42 0.42 0.50 0.44 0.37 0.34 0.42 0.30 0.22 0.22 0.10 0.27 0.30 0.32 0.35
-1I
0.59 0.42 0.49 0.49 0.59 0.51 0.43 0.40 0.50 0.37 0.26 0.26 0.11 0.31 0.35 0.36 0.41
-1M
0.59 0.42 0.49 0.49 0.59 0.51 0.43 0.40 0.50 0.37 0.26 0.26 0.11 0.31 0.35 0.36 0.41
Units
ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max
Sequential Delays
TCKO TDICK/TCKDI TRCK TCECK/TCKCE TSRCK/TCKSR TCINCK/TCKCIN Clock to AQ - DQ outputs 0.40 0.47 0.47 ns, Max
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
AX - DX input to CLK on A - D Flip Flops DX input to CLK when used as REV CE input to CLK on A - D Flip Flops SR input to CLK on A - D Flip Flops CIN input to CLK on A - D Flip Flops 0.41 0.21 0.42 0.20 -0.04 0.49 -0.19 0.16 0.16 0.49 0.24 0.51 0.23 -0.04 0.59 -0.19 0.18 0.19 0.49 0.31 0.51 0.23 -0.03 0.59 -0.19 0.18 0.26 ns, Min ns, Min ns, Min ns, Min ns, Min
Set/Reset
TSRMIN TRQ TCEO FTOG Notes:
1. 2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. These items are of interest for Carry Chain applications.
SR input minimum pulse width Delay from SR or REV input to AQ - DQ flip-flops Delay from CE input to AQ - DQ flip-flops Toggle frequency (for export control)
0.90 0.86 0.52 1265
0.90 1.03 0.63 1098
0.90 1.03 0.63 1098
ns, Min ns, Max ns, Max MHz
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 66: CLB Distributed RAM Switching Characteristics
Symbol Sequential Delays
TSHCKO TSHCKO_1 Clock to A - B outputs Clock to AMUX - BMUX outputs 1.26 1.38 1.54 1.68 1.54 1.68 ns, Max ns, Max
Description
Speed Grade -2I -1I -1M
Units
Setup and Hold Times Before/After Clock CLK
TDS/TDH TAS/TAH TWS/TWH TCECK/TCKCE A - D inputs to CLK Address An inputs to clock WE input to clock CE input to CLK 0.84 0.22 0.46 0.22 0.39 -0.04 0.42 -0.07 1.03 0.26 0.54 0.27 0.46 -0.02 0.51 -0.06 1.03 0.26 0.54 0.27 0.46 -0.02 0.51 -0.06 ns, Min ns, Min ns, Min ns, Min
Clock CLK
TMPW TMCP Notes:
1. 2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. TSHCKO also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path.
Minimum pulse width Minimum clock period
0.82 1.64
1.00 2.00
1.00 2.00
ns, Min ns, Min
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 67: CLB Shift Register Switching Characteristics
Symbol Sequential Delays
TREG TREG_MUX TREG_M31 Clock to A - D outputs Clock to AMUX - DMUX output Clock to DMUX output via M31 output 1.43 1.55 1.15 1.73 1.87 1.38 1.73 1.87 1.38 ns, Max ns, Max ns, Max
Description
Speed Grade -2I -1I -1M
Units
Setup and Hold Times Before/After Clock CLK
TWS/TWH TCECK/TCKCE TDS/TDH Clock CLK TMPW Notes:
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
WE input CE input to CLK A - D inputs to CLK
0.24 -0.04 0.27 -0.07 0.66 0.09
0.29 -0.02 0.33 -0.06 0.78 0.11
0.29 -0.02 0.33 -0.06 0.78 0.11
ns, Min ns, Min ns, Min
Minimum pulse width
0.70
0.85
0.85
ns, Min
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 68: Block RAM and FIFO Switching Characteristics
Symbol Block RAM and FIFO Clock to Out Delays
TRCKO_DO and TRCKO_DOR(1) Clock CLK to DOUT output (without output register)(2, 3) Clock CLK to DOUT output (with output register)(4, 5) 1.92 0.69 3.03 0.77 2.44 1.07 0.87 1.26 0.77 2.85 1.47 0.89 2.19 0.82 3.61 0.93 2.94 1.30 1.02 1.48 0.93 3.41 1.74 1.05 2.19 0.82 3.61 0.93 2.94 1.30 1.02 1.48 0.93 3.41 1.74 1.05 ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max
Description
Speed Grade -2I -1I -1M
Units
Clock CLK to DOUT output with ECC (without output register)(2, 3) Clock CLK to DOUT output with ECC (with output register)(4, 5) Clock CLK to DOUT output with Cascade (without output register)(2) Clock CLK to DOUT output with Cascade (with output register)(4) TRCKO_FLAGS TRCKO_POINTERS TRCKO_ECCR TRCKO_ECC Clock CLK to FIFO flags outputs(6) Clock CLK to FIFO pointer outputs(7)
Clock CLK to BITERR (with output register) Clock CLK to BITERR (without output register) Clock CLK to ECCPARITY in standard ECC mode Clock CLK to ECCPARITY in ECC encode only mode
Setup and Hold Times Before/After Clock CLK
TRCCK_ADDR/TRCKC_ADDR TRDCK_DI/TRCKD_DI ADDR inputs(8) DIN inputs(9) DIN inputs with ECC in standard mode(9) TRDCK_DI_ECC/TRCKD_DI_ECC DIN inputs with ECC encode only(9) TRCCK_EN/TRCKC_EN TRCCK_REGCE/TRCKC_REGCE TRCCK_SSR/TRCKC_SSR TRCCK_WE/TRCKC_WE TRCCK_WREN/TRCKC_WREN Block RAM Enable (EN) input CE input of output register Synchronous Set/ Reset (SSR) input Write Enable (WE) input WREN/RDEN FIFO inputs(10) 0.40 0.32 0.30 0.28 0.37 0.33 0.72 0.33 0.36 0.15 0.16 0.24 0.21 0.25 0.51 0.17 0.41 0.34 0.48 0.36 0.35 0.29 0.42 0.36 0.77 0.36 0.42 0.15 0.18 0.27 0.26 0.28 0.63 0.18 0.48 0.40 0.48 0.36 0.35 0.29 0.42 0.47 0.77 0.47 0.42 0.15 0.18 0.27 0.26 0.28 0.63 0.18 0.48 0.40 ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min
Reset Delays
TRCO_FLAGS Reset RST to FIFO Flags/Pointers(11) 1.26 1.48 1.48 ns, Max
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 68: Block RAM and FIFO Switching Characteristics (Cont'd)
Symbol Maximum Frequency
FMAX FMAX_CASCADE FMAX_FIFO FMAX_ECC Notes:
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. TRACE will report all of these parameters as TRCKO_DO. TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters. These parameters also apply to synchronous FIFO with DO_REG = 0. TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1. TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR. TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT. The ADDR setup and hold must be met when EN is asserted even though WE is deasserted. Otherwise, block RAM data corruption is possible. TRCKO_DI includes both A and B inputs as well as the parity inputs of A and B. These parameters also apply to RDEN. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
Description
Speed Grade -2I -1I -1M
Units
Block RAM in all modes Block RAM in cascade configuration FIFO in all modes Block RAM and FIFO in ECC configuration
500 450 500 375
450 400 450 325
450 400 450 325
MHz MHz MHz MHz
DSP48E Switching Characteristics
Table 69: DSP48E Switching Characteristics
Symbol Description Speed Grade -2I -1I -1M Units
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_{AA, BB, ACINA, BCINB}/ TDSPCKD_{AA, BB, ACINA, BCINB} TDSPDCK_CC/TDSPCKD_CC {A, B, ACIN, BCIN} input to {A, B} register CLK 0.21 0.23 0.16 0.31 0.26 0.30 0.20 0.37 0.26 0.30 0.20 0.50 ns ns
C input to C register CLK
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{AM, BM, ACINM, BCINM}/ TDSPCKD_{AM, BM, ACINM, BCINM} {A, B, ACIN, BCIN} input to M register CLK 1.44 0.19 1.71 0.19 1.71 0.19 ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{AP, BP, ACINP, BCINP}_M/ TDSPCKD_{AP, BP, ACINP, BCINP}_M TDSPDCK_{AP, BP, ACINP, BCINP}_NM/ TDSPCKD_{AP, BP, ACINP, BCINP}_NM TDSPDCK_CP/TDSPCKD_CP TDSPDCK_{PCINP, CRYCINP, MULTSIGNINP}/ TDSPCKD_{PCINP, CRYCINP, MULTSIGNINP} {A, B, ACIN, BCIN} input to P register CLK using multiplier {A, B, ACIN, BCIN} input to P register CLK not using multiplier C input to P register CLK {PCIN, CARRYCASCIN, MULTSIGNIN} input to P register CLK 2.74 -0.30 1.54 -0.10 1.42 -0.13 1.17 0.11 3.25 -0.30 1.83 -0.10 1.70 -0.13 1.31 0.11 3.25 -0.30 1.83 -0.10 1.70 -0.13 1.31 0.11 ns ns ns ns
Setup and Hold Times of the CE Pins
TDSPCCK_{CEA1A, CEA2A, CEB1B, {CEA1, CEA2A, CEB1B, CEB2B} input to CEB2B}/ {A, B} register CLK TDSPCKC_{CEA1A, CEA2A, CEB1A, CEB2B} TDSPCCK_CECC/TDSPCKC_CECC TDSPCCK_CEMM/TDSPCKC_CEMM CEC input to C register CLK CEM input to M register CLK 0.28 0.25 0.21 0.21 0.29 0.21 0.33 0.31 0.26 0.28 0.36 0.26 0.33 0.31 0.26 0.28 0.36 0.26 ns
ns ns
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 69: DSP48E Switching Characteristics (Cont'd)
Symbol
TDSPCCK_CEPP/TDSPCKC_CEPP
Description
CEP input to P register CLK
Speed Grade -2I
0.63 0.01
-1I
0.73 0.01
-1M
0.73 0.01
Units
ns
Setup and Hold Times of the RST Pins
TDSPCCK_{RSTAA, RSTBB}/ TDSPCKC_{RSTAA, RSTBB} TDSPCCK_RSTCC/ TDSPCKC_RSTCC TDSPCCK_RSTMM/ TDSPCKC_RSTMM TDSPCCK_RSTPP/TDSPCKC_RSTPP {RSTA, RSTB} input to {A, B} register CLK RSTC input to C register CLK RSTM input to M register CLK RSTP input to P register CLK 0.28 0.26 0.21 0.21 0.29 0.21 0.63 0.01 0.33 0.31 0.26 0.28 0.36 0.26 0.73 0.01 0.33 0.31 0.26 0.28 0.36 0.26 0.73 0.01 ns ns ns ns
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_M {A, B} input to {P, CARRYOUT} output using multiplier 3.22 1.77 1.67 3.84 2.22 2.08 3.84 2.22 2.08 ns ns ns
TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_NM {A, B} input to {P, CARRYOUT} output not using multiplier TDSPDO_{CP, CCRYOUT, CRYINP, CRYINCRYOUT} {C, CARRYIN} input to {P, CARRYOUT} output
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{AACOUT, BBCOUT} TDSPDO_{APCOUT, ACRYCOUT, AMULTSIGNOUT, BPCOUT, BCRYCOUT, BMULTSIGNOUT}_M TDSPDO_{APCOUT, ACRYCOUT, AMULTSIGNOUT, BPCOUT, BCRYCOUT, BMULTSIGNOUT}_NM TDSPDO_{CPCOUT, CCRYCOUT, CMULTSIGNOUT, CRYINPCOUT, CRYINCRYCOUT, CRYINMULTSIGNOUT} {A, B} input to {ACOUT, BCOUT} output {A, B} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier {A, B} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier {C, CARRYIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 1.12 3.22 1.31 3.84 1.31 3.84 ns ns
1.92
2.42
2.42
ns
1.82
2.28
2.28
ns
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_{ACINP, ACINCRYOUT, BCINP, BCINCRYOUT}_M TDSPDO_{ACINP, ACINCRYOUT, BCINP, BCINCRYOUT}_NM TDSPDO_{ACINACOUT, BCINBCOUT} TDSPDO_{ACINPCOUT, ACINCRYCOUT, ACINMULTSIGNOUT, BCINPCOUT, BCINCRYCOUT, BCINMULTSIGNOUT}_M TDSPDO_{ACINPCOUT, ACINCRYCOUT, ACINMULTSIGNOUT, BCINPCOUT, BCINCRYCOUT, BCINMULTSIGNOUT}_NM TDSPDO_{PCINP, CRYCINP, MULTSIGNINP, PCINCRYOUT, CRYCINCRYOUT, MULTSIGNINCRYOUT} {ACIN, BCIN} input to {P, CARRYOUT} output using multiplier {ACIN, BCIN} input to {P, CARRYOUT} output not using multiplier {ACIN, BCIN} input to {ACOUT, BCOUT} output {ACIN, BCIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier {ACIN, BCIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier {PCIN, CARRYCASCIN, MULTSIGNIN} input to {P, CARRYOUT} output 3.22 1.77 1.12 3.22 3.84 2.22 1.31 3.84 3.84 2.22 1.31 3.84 ns ns ns ns
1.92
2.42
2.42
ns
1.45
1.82
1.82
ns
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 69: DSP48E Switching Characteristics (Cont'd)
Symbol
TDSPDO_{PCINPCOUT, CRYCINPCOUT, MULTSIGNINPCOUT, PCINCRYCOUT, CRYCINCRYCOUT, MULTSIGNINCRYCOUT, PCINMULTSIGNOUT, CRYCINMULTSIGNOUT, MULTSIGNINMULTSIGNOUT}
Description
{PCIN, CARRYCASCIN, MULTSIGNIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output
Speed Grade -2I
1.60
-1I
2.02
-1M
2.02
Units
ns
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_{PP, CRYOUTP} TDSPCKO_{CRYCOUTP, PCOUTP, MULTSIGNOUTP} CLK (PREG) to {P, CARRYOUT} output CLK (PREG) to {CARRYCASCOUT, PCOUT, MULTSIGNOUT} output 0.48 0.53 0.56 0.62 0.56 0.62 ns ns
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_{PM, CRYOUTM} TDSPCKO_{PCOUTM, CRYCOUTM, MULTSIGNOUTM} CLK (MREG) to {P, CARRYOUT} output CLK (MREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 2.10 2.13 2.47 2.66 2.47 2.66 ns ns
Clock to Outs from Input Register Clock to Output Pins
TDSPCKO_{PA, CRYOUTA, PB, CRYOUTB}_M TDSPCKO_{PA, CRYOUTA, PB, CRYOUTB}_NM TDSPCKO_{PC, CRYOUTC} CLK (AREG, BREG) to {P, CARRYOUT} output using multiplier CLK (AREG, BREG) to {P, CARRYOUT} output not using multiplier CLK (CREG) to {P, CARRYOUT} output 3.57 2.11 2.11 4.23 2.63 2.62 4.23 2.63 2.62 ns ns ns
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUTA, BCOUTB} TDSPCKO_{PCOUTA, CRYCOUTA, MULTSIGNOUTA, PCOUTB, CRYCOUTB, MULTSIGNOUTB}_M TDSPCKO_{PCOUTA, CRYCOUTA, MULTSIGNOUTA, PCOUTB, CRYCOUTB, MULTSIGNOUTB}_NM TDSPCKO_{PCOUTC, CRYCOUTC, MULTSIGNOUTC} CLK (AREG, BREG) to {ACOUT, BCOUT} CLK (AREG, BREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier CLK (AREG, BREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier CLK (CREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 0.68 3.57 0.79 4.23 0.79 4.23 ns ns
2.27
2.82
2.82
ns
2.26
2.82
2.82
ns
Maximum Frequency
FMAX FMAX_PATDET FMAX_MULT_NOMREG FMAX_MULT_NOMREG_PATDET With all registers used With pattern detector Two register multiply without MREG Two register multiply without MREG with pattern detect 500 465 324 300 450 410 275 254 450 410 275 254 MHz MHz MHz MHz
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Configuration Switching Characteristics
Table 70: Configuration Switching Characteristics
Symbol Power-up Timing Characteristics
TPL TPOR TICCK TPROGRAM Program Latency Power-on-Reset CCLK (output) delay Program Pulse Width 3 10 50 400 250 3 10 50 400 250 3 10 50 400 250 ms, Max ms, Min/Max ns, Min ns, Min
Description
Speed Grade -2I -1I -1M
Units
Master/Slave Serial Mode Programming Switching(1)
TDCCK/TCCKD TDSCCK/TSCCKD TCCO FMCCK FMCCKTOL FMSCCK DIN Setup/Hold, slave mode DIN Setup/Hold, master mode DOUT Maximum Frequency, master mode with respect to nominal CCLK. Frequency Tolerance, master mode with respect to nominal CCLK. Slave mode external CCLK 4.0 0.0 4.0 0.0 7.5 100 50 100 4.0 0.0 4.0 0.0 7.5 100 50 100 5.0 0.0 5.0 0.0 7.5 100 50 100 ns, Min ns, Min ns, Max MHz, Max % MHz
SelectMAP Mode Programming Switching(1)
TSMDCCK/TSMCCKD TSMCSCCK/TSMCCKCS TSMCCKW/TSMWCCK TSMCKCSO TSMCO TSMCKBY FSMCCK FRBCCK FMCCKTOL TTAPTCK TTCKTAP TTCKTDO FTCK FTCKB SelectMAP Data Setup/Hold CS_B Setup/Hold RDWR_B Setup/Hold CSO_B clock to out (330 pull-up resistor required) CCLK to DATA out in readback CCLK to BUSY out in readback Maximum Frequency with respect to nominal CCLK Maximum Readback Frequency with respect to nominal CCLK Frequency Tolerance with respect to nominal CCLK 3.0 0.5 3.0 0.5 8.0 0.5 10 9.0 7.5 100 60 50 3.0 0.5 3.0 0.5 8.0 0.5 10 9.0 7.5 100 60 50 3.0 0.5 3.0 0.5 8.0 0.5 10 9.0 7.5 100 60 50 ns, Min ns, Min ns, Min ns, Min ns, Max ns, Max MHz, Max MHz, Max %
Boundary-Scan Port Timing Specifications
TMS and TDI Setup time before TCK TMS and TDI Hold time after TCK TCK falling edge to TDO output valid Maximum configuration TCK clock frequency Maximum boundary-scan TCK clock frequency 1.0 2.0 6 66 66 1.0 2.0 6 66 66 1.0 2.0 6 66 66 ns, Min ns, Min ns, Max MHz, Max MHz, Max
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics Table 70: Configuration Switching Characteristics (Cont'd)
Symbol BPI Master Flash Mode Programming Switching
TBPICCO(4) TBPIDCC/TBPICCD TINITADDR ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B outputs valid after CCLK rising edge Setup/Hold on D[15:0] data input pins Minimum period of initial ADDR[25:0] address cycles 10 3.0 0.5 3.0 10 3.0 0.5 3.0 10 3.0 0.5 3.0 ns ns CCLK cycles
Description
Speed Grade -2I -1I -1M
Units
SPI Master Flash Mode Programming Switching
TSPIDCC/TSPIDCCD TSPICCM TSPICCFC TFSINIT/TFSINITH DIN Setup/Hold before/after the rising CCLK edge MOSI clock to out FCS_B clock to out FS[2:0] to INIT_B rising edge Setup and Hold 4.0 0.0 10 10 2 4.0 0.0 10 10 2 5.0 0.0 10 10 2 ns ns ns s
CCLK Output (Master Modes)
TMCCKL TMCCKH Master CCLK clock minimum Low time Master CCLK clock minimum High time 3.0 3.0 3.0 3.0 3.0 3.0 ns, Min ns, Min
CCLK Input (Slave Modes)
TSCCKL TSCCKH FDCK TDMCCK_DADDR/TDMCKC_DADDR TDMCCK_DI/TDMCKC_DI TDMCCK_DEN/TDMCKC_DEN TDMCCK_DWE/TDMCKC_DWE TDMCKO_DO TDMCKO_DRDY Notes:
1. 2. 3. 4. Maximum frequency and setup/hold timing parameters are for 3.3V and 2.5V configuration voltages. To support longer delays in configuration, use the design solutions described in Virtex-5 FPGA User Guide. DO will hold until next DRP operation. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
Slave CCLK clock minimum Low time Slave CCLK clock minimum High time
2.0 2.0
2.0 2.0
2.0 2.0
ns, Min ns, Min
Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK
Maximum frequency for DCLK DADDR Setup/Hold DI Setup/Hold DEN Setup/Hold time DWE Setup/Hold time CLK to out of DO(3) CLK to out of DRDY 450 1.35 0.0 1.35 0.0 1.35 0.0 1.35 0.0 1.12 1.12 400 1.56 0.0 1.56 0.0 1.56 0.0 1.56 0.0 1.30 1.30 400 1.56 0.0 1.56 0.0 1.56 0.0 1.56 0.0 1.30 1.30 MHz ns ns ns ns ns ns
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Clock Buffers and Networks
Table 71: Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol
TBCCCK_CE/TBCCKC_CE(1) TBCCCK_S/TBCCKC_S(1)
Description
CE pins Setup/Hold S pins Setup/Hold All All
Devices
Speed Grade -2I
0.27 0.00 0.27 0.00 0.22
-1I
0.31 0.00 0.31 0.00 0.25
-1M
0.31 0.00 0.31 0.00 0.25
Units
ns ns ns
TBCCKO_O(2)
BUFGCTRL delay from I0/I1 to O
LX30T, LX85, LX110, LX110T, SX50T, FX70T, FX100T, and FX130T LX155T LX220T, LX330T, SX95T, SX240T, and FX200T
0.14 0.22
0.30 0.25
N/A N/A
ns ns
Maximum Frequency
LX30T, LX85, LX110, LX110T, SX50T, and FX70T(I) FMAX Global clock tree (BUFG) LX155T, FX70T(M), and FX100T FX130T LX220T, LX330T, SX95T, SX240T, and FX200T Notes:
1. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks. TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values.
667 600 500 500
600 550 450 450
N/A 550 N/A N/A
MHz MHz MHz MHz
2.
Table 72: Input/Output Clock Switching Characteristics (BUFIO)
Symbol
TBUFIOCKO_O
Description
Clock to out delay from I to O I/O clock tree (BUFIO)
Speed Grade -2I
1.16 710
-1I
1.29 644
-1M
1.29 644
Units
ns MHz
Maximum Frequency
FMAX
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 73: Regional Clock Switching Characteristics (BUFR)
Symbol Description Devices
LX30T, LX85, LX110, LX110T, SX50T, FX100T, and FX130T TBRCKO_O Clock to out delay from I to O FX70T LX155T LX220T, LX330T, SX95T, SX240T, and FX200T LX30T, LX85, LX110, LX110T, SX50T, FX70T, FX100T, and FX130T TBRCKO_O_BYP Clock to out delay from I to O with Divide Bypass attribute set LX155T LX220T, LX330T, SX95T, SX240T, and FX200T TBRDO_CLRO FMAX Propagation delay from CLR to O All Regional clock tree (BUFR) All
Speed Grade -2I
0.59 0.74 0.80 0.59 0.24 0.26 0.24 0.70 250
-1I
0.67 0.83 0.90 0.67 0.26 0.30 0.26 0.82 250
-1M
0.67 0.83 N/A N/A 0.26 N/A N/A 0.82 250
Units
ns ns ns ns ns ns ns ns MHz
Maximum Frequency
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
PLL Switching Characteristics
Table 74: PLL Specification
Symbol
FINMAX FINMIN FINJITTER FINDUTY
Description
Maximum Input Clock Frequency Minimum Input Clock Frequency Maximum Input Clock Period Jitter Allowable Input Duty Cycle: 19--49 MHz Allowable Input Duty Cycle: 50--199 MHz Allowable Input Duty Cycle: 200--399 MHz Allowable Input Duty Cycle: 400--499 MHz Allowable Input Duty Cycle: >500 MHz
Speed Grade -2I
710 19
-1I
645 19
-1M
645 19
Units
MHz MHz
<20% of clock input period or 1 ns Max 25/75 30/70 35/65 40/60 45/55 400 1200 1 4 120 400 1000 1 4 120 Note 1 400 1000 1 4 120 % % % % % MHz MHz MHz MHz ps
FVCOMIN FVCOMAX FBANDWIDTH TSTAPHAOFFSET TOUTJITTER TOUTDUTY TLOCKMAX FOUTMAX
Minimum PLL VCO Frequency Maximum PLL VCO Frequency Low PLL Bandwidth at High PLL Bandwidth at Jitter(2) Precision(3) Typical(1) Typical(1)
Static Phase Offset of the PLL Outputs PLL Output
PLL Output Clock Duty Cycle PLL Maximum Lock Time(4)
200 100 667 600 500 500 3.125
200 100 600 550 450 450 3.125
200 100 N/A 550 N/A N/A 3.125
ps s MHz MHz MHz MHz MHz
PLL Maximum Output Frequency for LX30T, LX85, LX110, LX110T, SX50T, and FX70T(I) devices PLL Maximum Output Frequency for LX155T, FX70T(M), and FX100T devices PLL Maximum Output Frequency for FX130T devices PLL Maximum Output Frequency for LX220T, LX330T, SX95T, SX240T, and FX200T devices
FOUTMIN TEXTFDVAR RSTMINPULSE FPFDMAX FPFDMIN TFBDELAY Notes:
1. 2. 3. 4. 5.
PLL Minimum Output Frequency(5) External Clock Feedback Variation Minimum Reset Pulse Width Maximum Frequency at the Phase Frequency Detector Minimum Frequency at the Phase Frequency Detector Maximum Delay in the Feedback Path
< 20% of clock input period or 1 ns Max 5 500 19 5 450 19 5 450 19 ns MHz MHz
3 ns Max or one CLKIN cycle
The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies. Values for this parameter are available in the Architecture Wizard. Includes global clock buffer. The LOCK signal must be sampled after TLOCKMAX. The LOCK signal is invalid after configuration or reset until the TLOCKMAX time has expired. Calculated as FVCO/128 assuming output duty cycle is 50%.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 75: PLL in PMCD Mode Switching Characteristics
Symbol
TPLLCCK_REL/TPLLCKC_REL TPLLCCKO CLKIN_FREQ_MAX CLKIN_FREQ_MIN CLKIN_DUTY_CYCLE
Description
REL Setup and Hold for all Outputs Maximum Clock Propagation Delay Maximum Input Frequency Minimum Input Frequency Allowable Input Duty Cycle: 1--49 MHz Allowable Input Duty Cycle: 50--199 MHz Allowable Input Duty Cycle: 200--399 MHz Allowable Input Duty Cycle: 400--499 MHz Allowable Input Duty Cycle: >500 MHz
Speed Grade -2I
0.00 0.60 4.6 710 1
-1I
0.00 0.60 5.2 645 1 25/75 30/70 35/65 40/60 45/55
-1M
0.00 0.60 5.2 645 1
Units
ns ns MHz MHz % % % % %
RES_REL_PULSE_MIN
Minimum Pulse Width for RST and REL
5
5
5
ns
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
DCM Switching Characteristics
Table 76: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode
Symbol Outputs Clocks (Low Frequency Mode)
F1XLFMSMIN F1XLFMSMAX F2XLFMSMIN F2XLFMSMAX FDVLFMSMIN FDVLFMSMAX FFXLFMSMIN FFXLFMSMAX CLKFX, CLKFX180 CLKDV(5) CLK2X, CLK2X180 CLK0, CLK90, CLK180, CLK270 32.00 135.00 64.00 270.00 2.0 90.00 32.00 160.00 CLKIN (using DLL outputs)(1, 3, 4) only)(2, 3, 4) 32.00 120.00 64.00 240.00 2.0 80.00 32.00 140.00 32.00 120.00 64.00 240.00 2.0 80.00 32.00 140.00 MHz MHz MHz MHz MHz MHz MHz MHz
Description
Speed Grade -2I -1I -1M
Units
Input Clocks (Low Frequency Mode)
FDLLLFMSMIN FDLLLFMSMAX FCLKINLFFXMSMIN FCLKINLFFXMSMAX FPSCLKLFMSMIN FPSCLKLFMSMAX PSCLK CLKIN (using DFS outputs 32.00 135.00 1.00 160.00 1.00 500.00 32.00 120.00 1.00 140.00 1.00 450.00 32.00 120.00 1.00 140.00 1.00 450.00 MHz MHz MHz MHz KHz MHz
Outputs Clocks (High Frequency Mode)
F1XHFMSMIN F1XHFMSMAX F2XHFMSMIN F2XHFMSMAX FDVHFMSMIN FDVHFMSMAX FFXHFMSMIN FFXHFMSMAX CLKFX, CLKFX180(5) CLKDV(5) CLK2X, CLK2X180 CLK0, CLK90, CLK180, CLK270 120.00 500.00 240.00 500.00 7.5 333.34 140.00 375.00 CLKIN (using DLL outputs)(1, 3, 4) only)(2)(3)(4)(5) 120.00 450.00 240.00 450.00 7.5 300.00 140.00 350.00 120.00 450.00 240.00 450.00 7.5 300.00 140.00 350.00 MHz MHz MHz MHz MHz MHz MHz MHz
Input Clocks (High Frequency Mode)
FDLLHFMSMIN FDLLHFMSMAX FCLKINHFFXMSMIN FCLKINHFFXMSMAX FPSCLKHFMSMIN FPSCLKHFMSMAX Notes:
1. 2. 3. 4. 5. DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input frequency. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within 5% (45/55 to 55/45). Only available for I-temperature conditions.
120.00 500.00
120.00 450.00 25.00 350.00 1.00 450.00
120.00 450.00 25.00 350.00 1.00 450.00
MHz MHz MHz MHz KHz MHz
CLKIN (using DFS outputs
25.00 375.00
PSCLK
1.00 500.00
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 77: Operating Frequency Ranges for DCM in Maximum Range (MR) Mode(5)
Symbol Outputs Clocks (Low Frequency Mode)
F1XMRMIN F1XMRMAX F2XMRMIN F2XMRMAX FDLLMRMIN FDLLMRMAX FFXMRMIN FFXMRMAX CLK0, CLK90, CLK180, CLK270 19.00 32.00 38.00 64.00 1.19 21.34 19.00 40.00 19.00 32.00 38.00 64.00 1.19 21.34 19.00 40.00 19.00 32.00 38.00 64.00 1.19 21.34 19.00 40.00 MHz MHz MHz MHz MHz MHz MHz MHz
Description
Speed Grade -2I -1I -1M
Units
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
Input Clocks (Low Frequency Mode)
FCLKINDLLMRMIN FCLKINDLLMRMAX FCLKINFXMRMIN FCLKINFXMRMAX FPSCLKMRMIN FPSCLKMRMAX Notes:
1. 2. 3. 4. 5. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input frequency. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within 5% (45/55 to 55/45). Maximum range is not available outside of I-temperature conditions.
CLKIN (using DLL outputs)(1, 3, 4) CLKIN (using DFS outputs only)(2, 3, 4)
19.00 32.00 1.00 40.00 1.00 270.00
19.00 32.00 1.00 40.00 1.00 240.00
19.00 32.00 1.00 40.00 1.00 240.00
MHz MHz MHz MHz KHz MHz
PSCLK
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 78: Input Clock Tolerances
Symbol Duty Cycle Input Tolerance (in %)
TDUTYCYCRANGE_1 TDUTYCYCRANGE_1_50 TDUTYCYCRANGE_50_100 TDUTYCYCRANGE_100_200 TDUTYCYCRANGE_200_400 TDUTYCYCRANGE_400 PSCLK and CLKIN PSCLK only < 1 MHz 1 - 50 MHz 50 - 100 MHz 100 - 200 MHz 200 - 400 MHz(4) 25 - 75 25 - 75 30 - 70 40 - 60 45 - 55 45 - 55 % % % % % %
Description
Frequency Range
Value
Units
> 400 MHz
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
TCYCLFDLL TCYCLFFX TCYCHFDLL TCYCHFFX TPERLFDLL TPERLFFX TPERHFDLL TPERHFFX CLKIN (using DLL outputs)(1) CLKIN (using DFS outputs)(2)
Speed Grade -2I
300.00 300.00
-1I
345.00 345.00
-1M
345.00 345.00
Units
ps ps
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
CLKIN (using DLL outputs)(1) CLKIN (using DFS outputs)(2) 150.00 150.00 173.00 173.00 173.00 173.00 ps ps
Input Clock Period Jitter (Low Frequency Mode)
CLKIN (using DLL outputs)(1) CLKIN (using DFS outputs)(2) 1.00 1.00 1.15 1.15 1.15 1.15 ns ns
Input Clock Period Jitter (High Frequency Mode)
CLKIN (using DLL outputs)(1) CLKIN (using DFS outputs)(2) 1.00 1.00 1.15 1.15 1.15 1.15 ns ns
Feedback Clock Path Delay Variation
TCLKFB_DELAY_VAR Notes:
1. 2. 3. 4. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. If both DLL and DFS outputs are used, follow the more restrictive specifications. This duty cycle specification does not apply to the GTP_DUAL to DCM or GTX_DUAL to DCM connection. The GTP transceivers drive the DCMs at the following frequencies: 320 MHz for -1I speed grade devices, or 375 MHz for -2I speed grade devices. The GTX transceivers drive the DCMs at the following frequencies: 450 MHz for -1I speed grade devices or 500 MHz for -2I speed grade devices.
CLKFB off-chip feedback
1.00
1.15
1.15
ns
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Output Clock Jitter
Table 79: Output Clock Jitter
Symbol Clock Synthesis Period Jitter
TPERJITT_0 TPERJITT_90 TPERJITT_180 TPERJITT_270 TPERJITT_2X TPERJITT_DV1 TPERJITT_DV2 TPERJITT_FX Notes:
1. Values for this parameter are available in the Architecture Wizard.
Description
Speed Grade -2I -1I -1M
Units
CLK0 CLK90 CLK180 CLK270 CLK2X, CLK2X180 CLKDV (integer division) CLKDV (non-integer division) CLKFX, CLKFX180
120 120 120 120 200 150 300 Note 1
120 120 120 120 230 180 345 Note 1
120 120 120 120 230 180 345 Note 1
ps ps ps ps ps ps ps ps
Output Clock Phase Alignment
Table 80: Output Clock Phase Alignment
Symbol Phase Offset Between CLKIN and CLKFB
TIN_FB_OFFSET TOUT_OFFSET_1X TOUT_OFFSET_2X TOUT_OFFSET_FX CLKIN/CLKFB 50 60 60 ps
Description
Speed Grade -2I -1I -1M
Units
Phase Offset Between Any DCM
Outputs(1)
140 150 160 160 200 220 160 200 220 ps ps ps
CLK0, CLK90, CLK180, CLK270 CLK2X, CLK2X180, CLKDV CLKFX, CLKFX180 DLL outputs(3) DFS outputs(4)
Duty Cycle
Precision(2)
150 150 180 180 180 180 ps ps
TDUTY_CYC_DLL TDUTY_CYC_FX Notes:
1. 2. 3. 4.
All phase offsets are with respect to group CLK1X. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if DUTY_CYCLE_CORRECTION = TRUE. The duty cycle distortion includes the global clock tree (BUFG). DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 81: Miscellaneous Timing Parameters
Symbol Time Required to Achieve LOCK
TDLL_240 TDLL_120_240 TDLL_60_120 TDLL_50_60 TDLL_40_50 TDLL_30_40 TDLL_24_30 TDLL_30 TFX_MIN TFX_MAX TDLL_FINE_SHIFT DLL output - Frequency range > 240 MHz(1) DLL output - Frequency range 120 - 240 DLL output - Frequency range 60 - 120 DLL output - Frequency range 50 - 60 DLL output - Frequency range 40 - 50 DLL output - Frequency range 30 - 40 DLL output - Frequency range 24 - 30 DLL output - Frequency range < 30 DFS outputs(2) Multiplication factor for DLL lock time with Fine Shift MHz(1) MHz(1) 80.00 250.00 900.00 1300.00 2000.00 3600.00 5000.00 5000.00 10.00 10.00 2.00 80.00 250.00 900.00 1300.00 2000.00 3600.00 5000.00 5000.00 10.00 10.00 2.00 80.00 250.00 900.00 1300.00 2000.00 3600.00 5000.00 5000.00 10.00 10.00 2.00 s s s s s s s s ms ms
Description
Speed Grade -2I -1I -1M
Units
MHz(1) MHz(1) MHz(1) MHz(1)
MHz(1)
Fine Phase Shifting
TRANGE_MS TRANGE_MR(3) Absolute shifting range in maximum speed mode Absolute shifting range in maximum range mode 7.00 10.00 7.00 10.00 7.00 10.00 ns ns
Delay Lines
TTAP_MS_MIN TTAP_MS_MAX TTAP_MR_MIN
(3)
Tap delay resolution (Min) in maximum speed mode Tap delay resolution (Max) in maximum speed mode Tap delay resolution (Min) in maximum range mode Tap delay resolution (Max) in maximum range mode
7.00 30.00 10.00 40.00
7.00 30.00 10.00 40.00
7.00 30.00 10.00 40.00
ps ps ps ps
TTAP_MR_MAX(3) Notes:
1. 2. 3.
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. Maximum range is not available outside of I-temperature conditions.
Table 82: Frequency Synthesis
Attribute
CLKFX_MULTIPLY CLKFX_DIVIDE
Min
2 1
Max
33 32
Table 83: DCM Switching Characteristics
Symbol
TDMCCK_PSEN/ TDMCKC_PSEN TDMCCK_PSINCDEC/ TDMCKC_PSINCDEC TDMCKO_PSDONE
Description
PSEN Setup/Hold PSINCDEC Setup/Hold Clock to out of PSDONE
Speed Grade -2I
1.35 0.00 1.35 0.00 1.12
-1I
1.56 0.00 1.56 0.00 1.30
-1M
1.56 0.00 1.56 0.00 1.30
Units
ns ns ns
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Virtex-5Q Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 84. Values are expressed in nanoseconds unless otherwise noted. Table 84: Global Clock Input to Output Delay Without DCM or PLL
Symbol Description Device Speed Grade -2I -1I -1M Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without DCM or PLL
TICKOF Global Clock and OUTFF without DCM or PLL XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
6.04 6.28 6.35 6.35 6.68 6.99 N/A 6.27 6.59 N/A 6.33 6.73 6.80 N/A
6.73 6.99 7.06 7.06 7.52 7.71 7.91 6.97 7.30 7.98 7.04 7.44 7.52 7.91
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 7.04 7.44 N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 85: Global Clock Input to Output Delay With DCM in System-Synchronous Mode
Symbol Description Device Speed Grade -2I -1I -1M Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in System-Synchronous Mode
TICKOFDCM Global Clock and OUTFF with DCM XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T Notes:
1. 2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. DCM output jitter is already included in the timing calculation.
2.56 2.63 2.69 2.69 2.74 2.83 N/A 2.69 2.64 N/A 2.74 2.59 2.67 N/A
2.93 3.00 3.06 3.06 3.10 3.18 3.37 3.05 3.00 3.36 3.12 3.00 3.07 3.27
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 3.12 3.00 N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 86: Global Clock Input to Output Delay With DCM in Source-Synchronous Mode
Symbol Description Device Speed Grade -2I -1I -1M Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in Source-Synchronous Mode
TICKOFDCM_0 Global Clock and OUTFF with DCM XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T Notes:
1. 2.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
3.71 3.86 3.92 3.92 4.18 4.41 N/A 3.91 4.16 N/A 3.96 4.10 4.29 N/A
4.15 4.29 4.36 4.36 4.62 4.85 5.04 4.35 4.59 5.11 4.41 4.53 4.74 5.03
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 4.41 4.53 N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
accessible IOB and CLB flip-flops are clocked by the global clock net. DCM output jitter is already included in the timing calculation.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 87: Global Clock Input to Output Delay With PLL in System-Synchronous Mode
Symbol Description Device Speed Grade -2I -1I -1M Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in System-Synchronous Mode
TICKOFPLL Global Clock and OUTFF with PLL XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T Notes:
1. 2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. PLL output jitter is included in the timing calculation.
2.30 2.49 2.53 2.53 2.60 2.74 N/A 2.36 2.29 N/A 2.71 2.70 2.75 N/A
2.70 2.88 2.92 2.92 3.01 3.12 3.27 2.76 2.69 3.34 3.10 3.10 3.17 3.35
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 3.10 3.10 N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 88: Global Clock Input to Output Delay With PLL in Source-Synchronous Mode
Symbol Description Device Speed Grade -2I -1I -1M Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in Source-Synchronous Mode
TICKOFPLL_0 Global Clock and OUTFF with PLL XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T Notes:
1. 2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. PLL output jitter is included in the timing calculation.
4.32 4.40 4.44 4.44 4.66 4.85 N/A 4.54 4.68 N/A 4.54 4.70 4.86 N/A
4.82 4.88 4.92 4.92 5.16 5.29 5.44 5.02 5.14 5.51 5.02 5.19 5.40 5.55
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 5.02 5.19 N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 89: Global Clock Input to Output Delay With DCM and PLL in System-Synchronous Mode
Symbol Description Device Speed Grade -2I -1I -1M Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM and PLL in System-Synchronous Mode
TICKOFDCM_PLL Global Clock and OUTFF with DCM and PLL XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T Notes:
1. 2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. DCM and PLL output jitter are already included in the timing calculation.
2.48 2.55 2.61 2.61 2.66 2.75 N/A 2.61 2.56 N/A 2.66 2.51 2.59 N/A
2.84 2.91 2.97 2.97 3.01 3.09 3.28 2.96 2.91 3.27 3.03 2.91 2.98 3.18
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 3.03 2.91 N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 90: Global Clock Input to Output Delay With DCM and PLL in Source-Synchronous Mode
Symbol Description Device Speed Grade -2I -1I -1M Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM and PLL in Source-Synchronous Mode
TICKOFDCM0_PLL Global Clock and OUTFF with DCM and PLL XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T Notes:
1. 2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. DCM and PLL output jitter are already included in the timing calculation.
3.63 3.78 3.84 3.84 4.10 4.33 N/A 3.83 4.08 N/A 3.88 4.02 4.21 N/A
4.06 4.20 4.27 4.27 4.53 4.76 4.95 4.26 4.50 5.02 4.32 4.44 4.65 4.94
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 4.32 4.44 N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Virtex-5Q Device Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 91. Values are expressed in nanoseconds unless otherwise noted. Table 91: Global Clock Setup and Hold without DCM or PLL
Symbol Description Device Speed Grade -2I -1I -1M Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard(1)
TPSFD/ TPHFD Full Delay (Legacy Delay or Default Delay) Global Clock and IFF(2) without DCM or PLL XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. IFF = Input Flip-Flop or Latch A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
1.60 -0.35 1.89 -0.49 1.88 -0.43 1.88 -0.43 2.36 -0.50 2.57 -0.74 N/A 1.74 -0.31 2.10 -0.44 N/A 2.06 -0.30 2.38 -0.42 2.59 -0.54 N/A
1.76 -0.35 2.09 -0.49 2.09 -0.43 2.09 -0.43 2.78 -0.49 2.86 -0.74 2.86 -0.56 1.93 -0.31 2.32 -0.44 2.28 0.18 2.35 -0.30 2.66 -0.42 2.95 -0.54 2.81 -0.43
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 2.35 -0.30 2.66 -0.42 N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2. 3.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 92: Global Clock Setup and Hold with DCM in System-Synchronous Mode
Symbol Description Device Speed Grade -2I -1I -1M Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard(1)
TPSDCM/ TPHDCM No Delay Global Clock and IFF(2) with DCM in System-Synchronous Mode XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include DCM CLK0 jitter. IFF = Input Flip-Flop or Latch Use IBIS to determine any duty-cycle distortion incurred using various standards.
1.70 -0.50 1.76 -0.43 1.76 -0.37 1.76 -0.37 2.16 -0.32 2.17 -0.27 N/A 1.76 -0.37 2.34 -0.41 N/A 1.86 -0.36 2.35 -0.51 2.48 -0.43 N/A
1.88 -0.50 1.95 -0.43 1.95 -0.37 1.95 -0.37 2.38 -0.32 2.44 -0.27 2.44 -0.10 1.95 -0.37 2.35 -0.41 2.54 -0.10 1.98 -0.36 2.49 -0.49 2.72 -0.42 2.43 -0.21
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 1.98 -0.36 2.49 -0.49 N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2. 3.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 93: Global Clock Setup and Hold with DCM in Source-Synchronous Mode
Symbol Description Device Speed Grade -2I -1I -1M Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard(1)
TPSDCM0/ TPHDCM0 No Delay Global Clock and IFF(2) with DCM in Source-Synchronous Mode XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include DCM CLK0 jitter. IFF = Input Flip-Flop or Latch Use IBIS to determine any duty-cycle distortion incurred using various standards.
0.27 0.62 0.24 0.76 0.24 0.82 0.24 0.82 0.14 1.08 0.21 1.31 N/A 0.25 0.82 0.24 1.06 N/A 0.14 0.86 0.21 1.00 0.21 1.19 N/A
0.27 0.66 0.24 0.80 0.24 0.87 0.24 0.87 0.16 1.13 0.22 1.36 0.22 1.55 0.25 0.86 0.24 1.11 0.21 1.62 0.14 0.92 0.21 1.05 0.24 1.25 0.16 1.55
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0.14 0.92 0.21 1.05 N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2. 3.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 94: Global Clock Setup and Hold with PLL in System-Synchronous Mode
Symbol Description Device Speed Grade -2I -1I -1M Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard(1)
TPSPLL/ TPHPLL No Delay Global Clock and IFF(2) with PLL in System-Synchronous Mode XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter. IFF = Input Flip-Flop or Latch Use IBIS to determine any duty-cycle distortion incurred using various standards.
1.68 -0.80 1.95 -0.62 1.96 -0.57 1.96 -0.57 2.09 -0.49 1.93 -0.36 N/A 2.07 -0.72 2.17 -0.80 N/A 1.90 -0.30 1.91 -0.40 1.95 -0.28 N/A
1.90 -0.79 2.09 -0.61 2.10 -0.57 2.10 -0.57 2.37 -0.47 2.09 -0.36 2.34 -0.21 2.20 -0.72 2.35 -0.79 2.33 -0.14 2.07 -0.30 2.09 -0.38 2.14 -0.24 2.29 -0.14
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 2.07 -0.30 2.09 -0.38 N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2. 3.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 95: Global Clock Setup and Hold with PLL in Source-Synchronous Mode
Symbol Description Device Speed Grade -2I -1I -1M Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard(1)
TPSPLL0/ TPHPLL0 No Delay Global Clock and IFF(2) with PLL in Source-Synchronous Mode XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter. IFF = Input Flip-Flop or Latch Use IBIS to determine any duty-cycle distortion incurred using various standards.
-0.33 1.22 -0.23 1.30 -0.24 1.34 -0.25 1.34 -0.12 1.56 -0.34 1.75 N/A -0.26 1.44 -0.26 1.58 N/A -0.10 1.44 -0.18 1.60 -0.11 1.76 N/A
-0.33 1.34 -0.22 1.39 -0.23 1.43 -0.23 1.43 -0.10 1.67 -0.30 1.80 -0.30 1.95 -0.25 1.53 -0.24 1.65 -0.31 2.02 -0.09 1.53 -0.18 1.71 -0.09 1.92 -0.10 2.06
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A -0.09 1.53 -0.18 1.71 N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2. 3.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 96: Global Clock Setup and Hold with DCM and PLL in System-Synchronous Mode
Symbol Description Device Speed Grade -2I -1I -1M Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard(1)
TPSDCMPLL/ TPHDCMPLL No Delay Global Clock and IFF(2) with DCM and PLL in System-Synchronous Mode XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0 driving BUFG. IFF = Input Flip-Flop or Latch Use IBIS to determine any duty-cycle distortion incurred using various standards.
1.89 -0.58 1.93 -0.51 1.93 -0.45 1.93 -0.45 2.31 -0.40 2.32 -0.35 N/A 1.94 -0.45 2.51 -0.49 N/A 2.03 -0.44 2.51 -0.59 2.64 -0.51 N/A
2.06 -0.58 2.13 -0.51 2.13 -0.45 2.13 -0.45 2.55 -0.40 2.61 -0.35 2.61 -0.18 2.14 -0.45 2.53 -0.49 2.70 -0.18 2.16 -0.44 2.66 -0.58 2.89 -0.51 2.59 -0.30
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 2.16 -0.44 2.66 -0.58 N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2. 3.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 97: Global Clock Setup and Hold with DCM and PLL in Source-Synchronous Mode
Symbol Description Device Speed Grade
-2I -1I
-1M
Units
Example Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin,(1) Using DCM, PLL, and Global Clock Buffer. For situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values shown in IOB Switching Characteristics. TPSDCMPLL_0/ TPHDCMPLL_0 No Delay Global Clock and IFF (2) with DCM and PLL in Source-Synchronous Mode XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. The timing values were measured using the fine-phase adjustment feature of the DCM. These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0 driving BUFG. Package skew is not included in these measurements. IFF = Input Flip-Flop
0.46 0.54 0.42 0.68 0.41 0.74 0.41 0.74 0.29 1.00 0.36 1.23 N/A 0.43 0.74 0.41 0.98 N/A 0.32 0.78 0.35 0.92 0.37 1.11 N/A
0.46 0.57 0.42 0.71 0.41 0.78 0.41 0.78 0.33 1.04 0.38 1.27 0.38 1.46 0.43 0.77 0.41 1.02 0.38 1.53 0.32 0.83 0.35 0.96 0.41 1.16 0.33 1.46
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0.32 0.83 0.35 0.96 N/A N/A
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-5Q FPGA sourcesynchronous transmitter and receiver data-valid windows. Table 98: Duty Cycle Distortion and Clock-Tree Skew
Symbol
TDCD_CLK TCKSKEW
Description
Global Clock Tree Duty Cycle Distortion(1) Global Clock Tree Skew(2) All
Device
Speed Grade -2I
0.12 0.22 0.43 0.50 0.50 0.85 1.07 N/A 0.44 0.72 N/A 0.42 0.84 0.84 N/A 0.10 0.07 0.25
-1I
0.12 0.22 0.45 0.51 0.51 0.88 1.10 1.29 0.45 0.74 1.36 0.43 0.86 0.86 1.29 0.10 0.08 0.25
-1M
0.12 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0.43 0.86 N/A N/A 0.10 0.08 0.25
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
XQ5VLX30T XQ5VLX85 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T XQ5VFX70T XQ5VFX100T XQ5VFX130T XQ5VFX200T
TDCD_BUFIO TBUFIOSKEW TDCD_BUFR Notes:
1.
I/O clock tree duty cycle distortion I/O clock tree skew across one clock region Regional clock tree duty cycle distortion
All All All
2.
These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 99: Package Skew (1)
Symbol
TPKGSKEW
Description
Package Skew(2)
Device
XQ5VLX30T(3) XQ5VLX85 XQ5VLX110 XQ5VLX110 XQ5VLX110T XQ5VLX155T XQ5VLX220T XQ5VLX330T XQ5VSX50T XQ5VSX95T XQ5VSX240T(3) XQ5VFX70T XQ5VFX70T XQ5VFX100T XQ5VFX100T XQ5VFX130T XQ5VFX200T(3)
Package
FF323 EF676 EF676 EF1153 EF1136 EF1136 EF1738 EF1738 EF665 EF1136 FF1738 EF665 EF1136 EF1136 EF1738 EF1738 FF1738
Value
127 142 142 173 163 147 156 155 103 176 161 102 153 144 172 181 164
Units
ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Notes:
1. 2. 3. Package trace length information is available for these device/package combinations. This information can be used to deskew the package. These values represent the worst-case skew between any two SelectIO resources in the package: shortest flight time to longest flight time from Pad to Ball (7.0 ps per mm). The EF package is not available for these devices.
Table 100: Sample Window
Symbol
TSAMP TSAMP_BUFIO Notes:
1. This parameter indicates the total sampling error of Virtex-5Q FPGA DDR input registers across voltage, temperature, and process. The characterization methodology uses the DCM to capture the DDR input registers' edges of operation. These measurements include: - CLK0 DCM jitter - DCM accuracy (phase offset) - DCM phase shift resolution These measurements do not include package or clock tree skew. This parameter indicates the total sampling error of Virtex-5Q FPGA DDR input registers across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers' edges of operation. These measurements do not include package or clock tree skew.
Description
Sampling Error at Receiver Pins(1) Sampling Error at Receiver Pins using BUFIO(2)
Device
All All
Speed Grade -2I
500 400
-1I
550 450
-1M
550 450
Units
ps ps
2.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 101: Source-Synchronous Pin-to-Pin Setup/Hold and Clock-to-Out
Symbol Description Speed Grade -2I -1I -1M Units
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
TPSCS/TPHCS Setup/Hold of I/O clock -0.54 1.72 -0.54 1.91 -0.54 1.91 ns
Pin-to-Pin Clock-to-Out Using BUFIO
TICKOFCS Clock-to-Out of I/O clock 4.82 5.40 5.40 ns
Revision History
The following table shows the revision history for this document.
Date
05/05/09 12/17/09
Version
1.0 2.0 Initial Xilinx release.
Description of Revisions
Changed the document classification from Preliminary Product Specification to Product Specification. Updated XQ5VSX240T, XQ5VFX70T, and XQ5VFX200T to production devices in Table 54 and Table 55. Updated package information for XQ5VFX200T and XQ5VSX240T in Table 99. Production release of XQ5VFX70T and XQ5VFX100T in the -1M speed grade. This includes changes to Table 54 and Table 55. Added a -1M column to any table with speed grades. Also updated the -2I speed grade software in Table 55 for the XQ5VLX220T and XQ5VSX95T device. Added -1(M) column to Table 4 including values for XQ5VFX70T and XQ5VFX100T. Revised maximum VOD in Table 8. Updated both minimum and maximum VOCM in Table 10. Updated minimum DVPPIN in Table 40. In Table 46, updated TJ4.25 and added note 5. In Table 51, added I-grade and Mgrade delineation for gain error, bipolar gain error, and ADCCLK revised AIDD maximum specification. Added note 1 to Table 57. In Table 71, added the FX70T (M) specification for the global clock tree (BUFG) FMAX. Added the FX70T (M) specification for the FOUTMAX to Table 74. Added note 5 to Table 76. Added note 5 to Table 77. Added note 3 to Table 81.
07/23/10
2.1
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE FAILSAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, "CRITICAL APPLICATIONS"). FURTHERMORE, XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL APPLICATIONS.
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